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參數(shù)資料
| 型號： | 15923 |
| 英文描述： | FDDI on Copper with AMD PHY Components The Effect of Local Buffer? 118KB (PDF) |
| 中文描述： | 與AMD的物理層組件的本地緩沖作用，銅FDDI的？ 118KB（PDF格式） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 118K |
| 代理商： | 15923 |
FDDI on Copper with AMD PHY Components
2
The transmit waveform going to the cable is required to
meet a template based on a differential P-ECL output
waveform, such as at the PDT (ENDEC) outputs. This
means that AMD parts can be used to drive the STP ca-
ble directly (source terminations should be added as re-
quired by the IOS specifications). Also, the attenuated
signal coming out of the cable at the receiver end is suffi-
cient to allow clock and data recovery by the PDR (EDS)
without any need for amplification.
Transmitter Interface
The main coupling component to the cable is a trans-
former, which should be designed for the speed (rise
and fall time) and the frequency spectrum of the FDDI
signal. Figure 2 shows the data path. The transformer
shown is a 1:1 transformer with center taps made by
Pulse Engineering, Inc. R1 and R2 are biasing resistors
for the output driver stage inside the PDT (ENDEC). The
output voltages are roughly 3 volts for “LOW” and 4 volts
for “HIGH”, therefore the resistor values can be calcu-
lated from the average DC current: 3.5 V/R1 = 10 to 20
mA. R3 and R4 combined with the output impedance of
the driver and with the transformer series impedance
form the cable termination (150 ohms) at the transmitter
end. R3 and R4 will reduce the output signal to the cable
by a factor of two. The PDT output driver sees a differen-
tial impedance of about 300 ohms in parallel with the
540 ohm biasing resistors. This requires less than its full
driving capability of 100 ohms differential.
IOS specifies no precompensation at the transmitter
end in order to minimize high frequency power levels in
the transmitted signal spectrum, which improves the
FCC-related performance.
Receiver Interface
The main coupling component at the receiver end is also
the transformer. Figure 3 shows the data path. R4, R5
and R6 are bias resistors to bring the input stage of the
PDR (EDS) to its DC operating point of about 3.5 volts.
R5 provides a small offset voltage between RX and RY
to keep the inputs (and outputs) stable in the absence of
a carrier. The bias voltage level is isolated from the
transformer secondary by C3 and C4. It is also possible
to include the transformer in the DC path in order to
avoid the need for capacitors C3 and C4. In this case a
two-transformer option is a better choice. The R1, R2
and R3//R5 combination, and the parallel loading of Link
Detect (not shown) give the proper cable termination at
the receiver end (150 ohms). R1 and R2 with their paral-
lel capacitors C1 and C2 form a high-pass filter that
compensates for the high-frequency attenuation and
phase shift in the cable. There are many possible cor-
rect schemes for compensation. AMD’s parts can run a
100 meter link without compensation in most cases, pro-
vided the signal is not deteriorated by low performance
transformers or external noise. However, in the interest
of providing a robust implementation over the IOS speci-
fication, compensation has been included.
TY
R3
68
Either one 1:1
transformer with center
taps (as shown), or two
simple 1:1 transformers
R4
68
R1
270
R2
270
T1
FTP 4.0
STP 150
TX
15923A-002A
Am79865
Physical
Data
Transmitter
(PDT)
Figure 2. Transmitter Interface for Data Out
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