參數(shù)資料
型號(hào)： 1337DVGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： REAL TIME CLOCK, PDSO8
封裝： 3 MM, ROHS COMPLIANT, MSOP-8
文件頁(yè)數(shù)： 6/24頁(yè)
文件大?。?/td> 362K
代理商： 1337DVGI
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
IDT REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
14
IDT1337
REV J 111009
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: SCL only.
Note 3: SDA, INTA, and SQW/INTB.
Note 4: ICCA—SCL clocking at maximum frequency = 400 kHz, VIL = 0.0V, VIH = VCC.
Note 5: Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC.
Note 6: SQW enabled.
Note 7: Specified with the SQW function disabled by setting INTCN = 1.
Note 8: Using recommended crystal on X1 and X2.
Note 9: The device is fully accessible when 1.8 < VCC < 5.5 V. Time and date are maintained when 1.3 V < VCC <
1.8 V.
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 12: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > to 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) +
tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released.
Note 14: CB—total capacitance of one bus line in pF.
Note 15: Guaranteed by design. Not production tested.
Rise Time of Both SDA and SCL
Signals, Note 14
tR
Fast Mode
20 + 0.1CB
300
ns
Standard Mode
20 + 0.1CB
1000
Fall Time of Both SDA and SCL Signals,
Note 14
tF
Fast Mode
20 + 0.1CB
300
ns
Standard Mode
20 + 0.1CB
300
Setup Time for STOP Condition
tSU:STO
Fast Mode
0.6
s
Standard Mode
4.0
Capacitive Load for Each Bus Line,
Note 14
CB
400
pF
I/O Capacitance (SDA, SCL)
CI/O
Note 15
10
pF
32.768 kHz Clock Accuracy with
External Crystal
TA=25°C
VCC=3.3 V
±10
ppm
32.768 kHz Clock Accuracy with
Internal Crystal
TA=25°C
VCC=3.3 V
(crystal accuracy
±20ppm)
±30
ppm
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
相關(guān)PDF資料
PDF描述
1338-31DCGI 1 TIMER(S), REAL TIME CLOCK, PDSO8
1339-2DVGI 1 TIMER(S), REAL TIME CLOCK, PDSO8
1339-31DCGI8 1 TIMER(S), REAL TIME CLOCK, PDSO8
13715-806-XTD 300 MHz, OTHER CLOCK GENERATOR, PDSO16
1374610-3 INTERCONNECTION DEVICE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
1337DVGI8 制造商:Integrated Device Technology Inc 功能描述:REAL TIME CLOCK SERL 8TSSOP - Tape and Reel
1337G0 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC
1337G1 功能描述:重負(fù)荷電源連接器 PCB45 HORIZ (TOP) RA LP CONT. RoHS:否 制造商:Hirose Connector 系列:PS2 產(chǎn)品類型:Connectors 位置/觸點(diǎn)數(shù)量: 端接類型:Crimp 觸點(diǎn)材料: 觸點(diǎn)電鍍:Gold 電壓額定值: 電流額定值:300 A 附件類型:
1337G2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC
1337GCSRI 功能描述:實(shí)時(shí)時(shí)鐘 實(shí)時(shí)時(shí)鐘 with Embedded Crystal RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*