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參數(shù)資料
| 型號： | 1337DVGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | REAL TIME CLOCK, PDSO8 |
| 封裝： | 3 MM, ROHS COMPLIANT, MSOP-8 |
| 文件頁數(shù)： | 24/24頁 |
| 文件大小： | 362K |
| 代理商： | 1337DVGI |
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
IDT REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
9
IDT1337
REV J 111009
I2C Serial Data Bus
The IDT1337 supports the I2C bus protocol. A device that
sends data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The device that controls
the message is called a master. The devices that are
controlled by the master are referred to as slaves. A master
device that generates the serial clock (SCL), controls the
bus access, and generates the START and STOP conditions
must control the bus. The IDT1337 operates as a slave on
the I2C bus. Within the bus specifications, a standard mode
(100 kHz maximum clock rate) and a fast mode (400 kHz
maximum clock rate) are defined. The IDT1337 works in
both modes. Connections to the bus are made via the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see the “Data
Transfer on I2C Serial Bus” figure):
Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data valid: The state of the data line represents valid data
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The data on
the line must be changed during the LOW period of the clock
signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions are
not limited, and are determined by the master device. The
information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
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| 1339-2DVGI | 1 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 1339-31DCGI8 | 1 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 13715-806-XTD | 300 MHz, OTHER CLOCK GENERATOR, PDSO16 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 1337DVGI8 | 制造商:Integrated Device Technology Inc 功能描述:REAL TIME CLOCK SERL 8TSSOP - Tape and Reel |
| 1337G0 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| 1337G1 | 功能描述:重負(fù)荷電源連接器 PCB45 HORIZ (TOP) RA LP CONT. RoHS:否 制造商:Hirose Connector 系列:PS2 產(chǎn)品類型:Connectors 位置/觸點(diǎn)數(shù)量: 端接類型:Crimp 觸點(diǎn)材料: 觸點(diǎn)電鍍:Gold 電壓額定值: 電流額定值:300 A 附件類型: |
| 1337G2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| 1337GCSRI | 功能描述:實(shí)時時鐘 實(shí)時時鐘 with Embedded Crystal RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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