參數(shù)資料
型號(hào)： 101-0788
廠商： Rabbit Semiconductor
文件頁(yè)數(shù)： 74/90頁(yè)
文件大?。?/td> 0K
描述： COMPUTER SGL-BOARD OP6600 W/SRAM
標(biāo)準(zhǔn)包裝： 1
系列： SBC
模塊/板類型： 單板計(jì)算機(jī)模塊
適用于相關(guān)產(chǎn)品： OP6600
其它名稱： 101-788
101-788-ND
72
Intellicom (OP6600/OP6700)
The current drain on the battery in a battery-backed circuit must be kept at a minimum.
When the Intellicom is not powered, the battery keeps the SRAM memory contents and
the real-time clock (RTC) going. The SRAM has a powerdown mode that greatly reduces
power consumption. This powerdown mode is activated by raising the chip select (CS)
signal line. Normally the SRAM requires Vcc to operate. However, only 2 V is required
for data retention in powerdown mode. Thus, when power is removed from the circuit, the
battery voltage needs to be provided to both the SRAM power pin and to the CS signal
line. The CS control circuit accomplishes this task for the CS signal line.
In a powered-up condition, the CS control circuit must allow the processor’s chip select
signal /CS1 to control the SRAM’s CS signal /CSRAM. So, with power applied, /CSRAM
must be the same signal as /CS1, and with power removed, /CSRAM must be held high
(but only needs to be battery voltage high). Q5 and Q6 are MOSFET transistors with
opposing polarity. They are both turned on when power is applied to the circuit. They
allow the CS signal to pass from the processor to the SRAM so that the processor can peri-
odically access the SRAM. When power is removed from the circuit, the transistors will
turn off and isolate /CSRAM from the processor. The isolated /CSRAM line has a 100 k
pullup resistor to VRAM (R29). This pullup resistor keeps /CSRAM at the VRAM voltage
level (which under no power condition is the backup battery’s regulated voltage at a little
more than 2 V).
Transistors Q5 and Q6 are of opposite polarity so that a rail-to-rail voltage can be passed.
When the /CS1 voltage is low, Q5 will conduct. When the /CS1 voltage is high, Q6 will
conduct. It takes time for the transistors to turn on, creating a propagation delay. This
delay is typically very small, about 10 ns to 15 ns.
The signal that turns the transistors on is a high on the processor’s reset line, /RES. When
the Intellicom is not in reset, the reset line will be high, turning on n-channel Q5 and Q7.
Q7 is a simple inverter needed to turn on Q6, a p-channel MOSFET. When a reset occurs,
the /RES line will go low. This will cause C14 to discharge through R32 and R34. This
small delay (about 160 s) ensures that there is adequate time for the processor to write
any last byte pending to the SRAM before the processor puts itself into a reset state. When
coming out of reset, CS will be enabled very quickly because D1 conducts to charge
capacitor C14.
相關(guān)PDF資料
PDF描述
046232116103800 CONN FFC/FPC 16POS 1MM R/A SMD
346-048-540-804 CARDEDGE 48POS DUAL .125 GREEN
346-048-540-802 CARDEDGE 48POS DUAL .125 GREEN
346-048-540-204 CARDEDGE 48POS DUAL .125 GREEN
346-048-540-202 CARDEDGE 48POS DUAL .125 GREEN
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