參數(shù)資料
型號(hào)： 0W344-005-XTP
廠商： ON SEMICONDUCTOR
元件分類： 數(shù)字信號(hào)處理
英文描述： BelaSigna 200 - Single-Chip Audio Processing System; Package: 52 PIN QFN 8x8; No of Pins: 52; Container: Tape and Reel; Qty per Container: 1000
中文描述： 0-BIT, 33 MHz, MIXED DSP, QCC52
封裝： 8 X 8 MM, QFN-52
文件頁(yè)數(shù)： 18/43頁(yè)
文件大小： 1426K
代理商： 0W344-005-XTP
BelaSigna 200
Two analog outputs designed to drive external amplifiers are also available.
Figure 13: Output Stage
8.3 Clock-Generation Circuitry
BelaSigna 200 operates with two main clock domains: a domain running on the system clock (SYS_CLK) and a domain running on the
main clock (MCLK). SYS_CLK can either be internally generated or externally delivered. It is used to drive all on-chip processors such
as the RCore, the WOLA coprocessor and the IOP. MCLK is generated by division of SYS_CLK and is used to drive all A/D converters,
D/A converters and external interfaces (except SPI, PCM, I
2S, and GPIO interfaces). The division factor used to create the desired
MCLK from SYS_CLK is configurable to support external clocks with a wide range of frequencies.
The sampling frequency of all A/D converters and D/A converters also depends on MCLK. When MCLK is 1.28MHz, sampling
frequencies in the interval 10.7kHz to 20kHz can be selected. Sampling frequencies up to 60kHz can be obtained with other MCLK
frequencies.
8.4 Battery Monitor
A programmable on-chip battery monitor is available for power management. The battery monitor works by incrementing a counter
value every time the battery voltage goes below a desired, configurable threshold value. This counter value can be used in an
application-specific power-management algorithm running on the RCore. The RCore can initiate any desired actions in case the battery
hits a predetermined value.
8.5 Multi-Chip Sample Clock Synchronization
BelaSigna 200 allows MCLK synchronization between two or more BelaSigna 200 chips connected in a multi-chip configuration.
Samples on multiple chips occur at the same instant in time. This is useful in applications using microphone arrays where synchronous
sampling is required. The sample clock synchronization is enabled using a control bit and a GPIO assignment that brings all MCLKs
across chips to zero phase at the same instant in time.
Rev. 16 | Page 25 of 43 | www.onsemi.com
相關(guān)PDF資料
PDF描述
0W588-002-XUA BelaSigna 200 - Single-Chip Audio Processing System; Package: WLCSP 40, 3.8x2.3; No of Pins: 40; Container: Tape and Reel; Qty per Container: 5000
0W633-001-XTP BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 57, 5x5; No of Pins: 57; Container: Tape and Reel; Qty per Container: 5000
0W888-002-XTP BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 64, 7x7; No of Pins: 64; Container: Tape and Reel; Qty per Container: 1500
0X860 OSCILLOSCOPE 100MHz ANALOGUE
2-5174339-5 68 CONTACT(S), MALE, STRAIGHT TELECOM AND DATACOM CONNECTOR, SOLDER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
0W588-002-XUA 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC BELASIGNA 200 WLCSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
0W589-005-XDS 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC AUDIO AD/DA RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
0W589-007-XDS 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC AUDIO AD/DA RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
0W598001EVK 制造商:ON Semiconductor 功能描述:B250 EDK SGL PURCH - Bulk
0W633-001-XTP 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC BELASIGNA 250 CABGA 5X5 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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