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參數(shù)資料
| 型號： | 030_PCI |
| 英文描述： | Using a PCI Bus as the I/O Bus on an Am29030 Microprocessor Design |
| 中文描述： | 用的I / O上Am29030微處理器設(shè)計的PCI總線總線 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 352K |
| 代理商： | 030_PCI |
AMD
5
Title
Refresh Timer
The refresh timer is exactly as described in the
EZ-030
Demonstration Board Theory of Operation application
note, consisting of a 7-bit timer with the eighth bit serving
as a REFRESH_REQ bit, which remembers that a re-
fresh needs to be arbitrated by the main memory system
arbiter. The counter will continue counting towards the
next refresh interval.
Serial Port
If used, the serial port can be exactly the same as de-
scribed in the
EZ-030 Demonstration Board Theory of
Operation application note.
TIMING AND WORST-CASE ISSUES
This design assumes that the PGA Am29030 proces-
sor’s Scalable Clocking
t feature is used, resulting in a
32-MHz processor with a 16-MHz external memory and
PCI bus interface. The worst-case timing in this design
then occurs in the memory system around a single-cycle
read at 16 MHz. The delay must be set at 20 ns for the
CAS pulse generation while 12 ns is the best time of a
MACH220 device for the combinatorial delay, making
CAS fall at 32 ns into the cycle. CAS access time is 20
ns. A set up of 9 ns makes an access time of 61 ns for a
62.5-ns cycle at 16 MHz. If additional setup or CAS ac-
cess time is needed, then the RAS/CAS decode can be
accomplished in a separate, faster decode PAL device.
The DELAY signal from the delay line can be used in this
PAL device, with the other state lines going to the faster
decode PAL device. Additionally, faster address multi-
plexers can be used, such as 74F or AS parts, instead of
the 74LS157s. This reduces the delay from 12 ns to 6 ns
and decreases the delay line requirement to 15 ns, gain-
ing an additional 5 ns on CAS access. Use of these fast-
er 74F/AS157s then requires 33-ohm series dampening
resistors before the DRAMs.
The PCI bus from the initiator side meets the setup times
up to 25 MHz, but the CLK to Q delays on the beginning
of edges are not to the delay specification. This is really
not of consequence to this design because the bus is
running slower than the maximum of 33 MHz. This slow-
er speed allows a more relaxed timing as well as board
layout in the final analysis. The rest of the paths, includ-
ing to and from the processor and the surrounding con-
trol logic, have wide margins of setup and hold that can
be used.
PCI BUS SIGNAL QUALITY
The PCI bus is defined to be a current-driven reflected-
wave transmission line. However, all the drivers
(74F24x and MACH device) used in this design to drive
the PCI bus signals are voltage drivers, and therefore,
incident-wave drivers. Reflected-wave drivers have to
settle the bus and therefore have two times the trans-
mission line distance to settle, but incident-wave drivers
have only one times the transmission line time distance.
This makes up for some of the clock-to-Q time of the
74F24x parts. The input threshold levels and the final
output drive levels on the PCI bus are TTL-compatible,
which means the 74F24x and MACH device drivers are
compatible. When laying out the design, the best layout
is the MACH device, buffers, and PAL devices on one
end of the transmission line, and the sockets for the PCI
bus in line towards the opposite end.
The PCI bus allows 10 loads of 10 pF per load maximum
at 33 MHz. This design uses six loads for the three slots.
The three-way load of the 74F24x and PAL devices then
represent about 35 pF, making up the other four loads.
At 16 MHz, though, this requirement could be easily re-
laxed if needed.
SUGGESTED REFERENCE
Bank Interleaved Memory System for an Am29030
Microprocessor application note, order# 18478, Ad-
vanced Micro Devices
EZ-030 Demonstration Board Theory of Operation
application note, order# 17580, Advanced Micro De-
vices
PCI Local Bus Specification, Revision 2.0
PCI Special Interest Group
M/S HF3–15A
5200 N. E. Elam Young Parkway
Hillsboro, Oregon 97124–6497
(503) 696–2000
Appendix A. Schematics
The schematics for this design are shown on the pages
that follow.
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| 0702XTEXFREQ3 | CRYSTAL OSCILLATOR, CLOCK, 32 MHz - 80 MHz, TTL OUTPUT |
| 0702XTXBFREQ3 | CRYSTAL OSCILLATOR, CLOCK, 32 MHz - 80 MHz, TTL OUTPUT |
| 0702XTXXFREQ2 | CRYSTAL OSCILLATOR, CLOCK, 12.1 MHz - 32 MHz, TTL OUTPUT |
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