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參數資料
| 型號： | 030_PCI |
| 英文描述： | Using a PCI Bus as the I/O Bus on an Am29030 Microprocessor Design |
| 中文描述： | 用的I / O上Am29030微處理器設計的PCI總線總線 |
| 文件頁數： | 12/25頁 |
| 文件大小： | 352K |
| 代理商： | 030_PCI |
AMD
2
Title
THEORY OF OPERATIONS
As discussed in the introduction, this design is a modifi-
cation of the original EZ-030 board design. The major
change is that the three control PAL devices of the
EZ-030 board design are merged into one large control
PAL device, the MACH220 device, shown in the sche-
matic on page 8. Pages 9 through 12 show the need
of multiplexing the address and data bus together, and
pages 13 through 15 depict the three separate PCI con-
nectors.
Figures 1 and 2 show block diagrams for the original and
modified board designs, respectively.
The PCI bus is a multiplexed address, data, and control
bus to conserve on pins. The Am29030 processor is not
a multiplexed address and data bus part, so in the sche-
matic on page 12 , the 12 octal parts required to do the
address/data multiplexing are shown. U20 through U23,
74F244s, support placing the initial address in the first
clock cycle of the frame. (Note that the upper four bits,
A31–A28, are driven onto the PCI bus with 0s. These
bits are used on the local Am29030 processor side to
decode the various PCI bus cycles that are to be accom-
plished.)
U16 through U19, 74F245s, are the data buffers used to
input or output the data off or onto the PCI bus. These
parts will be used for Am29030 processor PCI bus
cycles, as well as when another PCI bus master is using
the DRAM memory.
If another bus master takes over the PCI bus and wants
to perform a DRAM memory cycle, the parts U24
through U27 capture the address on the first clock cycle
of the FRAME signal. The parts are 20L8s used to cap-
ture addresses A31–A10, A1, and A0 in a clock-enabled
register configuration. The equations for the 20L8s are
in Appendix B. The address bits A9–A2 are captured in a
22V10, which is a combination clock-enabled register
and a counter that supports the burst feature that PCI
has defined and enables the maximum throughput al-
lowed. This PAL device also detects an upper address
bit carry if the requesting master tries to burst across a
1K address boundary, which is then used by the PCI
controller to signal a STOP condition on the PCI bus.
This then is the full address and data support for both
bus master and bus slave.
The schematics shown on pages 13 through 15 of this
document show the PCI connectors. With the exception
of the interrupts and the bus request/grant signals being
point to point, all the other signals are bused in common.
Each slot is given its own interrupt to the processor from
the INTA of the PCI bus. Interrupts on the PCI bus are
negative True and level sensitive so they fit nicely to the
Am29030 processor interrupt input structure without a
need for additional interrupt controllers. Each bus re-
quest and grant is given to the MACH220 device to arbi-
trate the bus. All the power pins of the PCI connector in
this design are for 5 V; 3.3 V is not considered.
MACH220 DEVICE
The heart of the design is the MACH220 device, shown
in the schematic on page 8. Internally this part can be
subdivided into the following categories:
Bus arbitration
PCI control signals
Memory control
RAS and CAS decode
Refresh timer
Each of these parts is detailed in the following sections.
Bus Arbitration
The bus arbiter in this design “parks” the Am29030 pro-
cessor on the bus with a PROC_BGRT unless any of the
PCI_BREQx’s become valid. When a PCI_BREQx be-
comes valid, then the PROC_BGRT is lowered and the
arbiter waits for the REQ (Am29030 processor memory
request) to be released for at least 2 clock cycles. At that
point, the highest level PCI_BREQx is arbitrated and its
corresponding PCI_BGRTx is issued. This grant is held
until the PCI_BREQx goes away, the PCI_FRAME is re-
leased, and the last IRDY and TRDY have been issued.
If another PCI_BREQx is active, then the arbiter will
move to the highest new PCI_BREQx. If no other
PCI_BREQx is active, then the PROC_BGRT is issued
again and the whole cycle starts over. No attempt is
made to make a rotating-priority arbiter, although that
could be accomplished in the buried macros of the
MACH220 device. This arbiter simply functions as a
fixed-priority level arbiter.
PCI Control Signals
This section has the largest number of equations. Some
of them are for support when the Am29030 processor is
the bus master, while some of them are for the slave
memory interface. Address bit A31 is the magic control
bit that determines whether the Am29030 processor
stays local to the memory subsystem or goes to the PCI
bus. If A31=0, then the Am29030 processor will stay in
local memory section; if A31=1, then an external PCI ac-
cess is started.
When the Am29030 processor is a bus master and goes
to the PCI bus to access a peripheral, A31=1 and
PROC_BGRT is True. PROC_BGRT controls the three-
state of the PCI_FRAME, PCI_IRDY, and PCI_C_BEx
control lines. If A31=1 and PROC_BGRT is True, a
PCI_FRAME signal is generated on the first line of the
equations and is then held True if the Am29030 proces-
sor is bursting on the bus (BURST True).
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| 030R0090U | 功能描述:可復位保險絲 30V .9A 5.9s RoHS:否 制造商:Bourns 電流額定值: 電阻:7.5 Ohms 最大直流電壓: 保持電流:0.1 A 安裝風格:SMD/SMT 端接類型:SMD/SMT 跳閘電流:0.6 A 引線間隔: 系列:MF-PSHT 工作溫度范圍:- 40 C to + 125 C |
| 030R0090WR | 功能描述:可復位保險絲 30V .9A 5.9s RoHS:否 制造商:Bourns 電流額定值: 電阻:7.5 Ohms 最大直流電壓: 保持電流:0.1 A 安裝風格:SMD/SMT 端接類型:SMD/SMT 跳閘電流:0.6 A 引線間隔: 系列:MF-PSHT 工作溫度范圍:- 40 C to + 125 C |
| 030R0110U | 功能描述:可復位保險絲 30V 1.1A 6.6s RoHS:否 制造商:Bourns 電流額定值: 電阻:7.5 Ohms 最大直流電壓: 保持電流:0.1 A 安裝風格:SMD/SMT 端接類型:SMD/SMT 跳閘電流:0.6 A 引線間隔: 系列:MF-PSHT 工作溫度范圍:- 40 C to + 125 C |
| 030R0110WR | 功能描述:可復位保險絲 30V 1.1A 6.6s RoHS:否 制造商:Bourns 電流額定值: 電阻:7.5 Ohms 最大直流電壓: 保持電流:0.1 A 安裝風格:SMD/SMT 端接類型:SMD/SMT 跳閘電流:0.6 A 引線間隔: 系列:MF-PSHT 工作溫度范圍:- 40 C to + 125 C |
| 030R0135U | 功能描述:可復位保險絲 30V 1.35A 7.3s RoHS:否 制造商:Bourns 電流額定值: 電阻:7.5 Ohms 最大直流電壓: 保持電流:0.1 A 安裝風格:SMD/SMT 端接類型:SMD/SMT 跳閘電流:0.6 A 引線間隔: 系列:MF-PSHT 工作溫度范圍:- 40 C to + 125 C |
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