參數(shù)資料
型號: μPD78F9217Y
廠商: NEC Corp.
英文描述: 8 Bit Single Chip Microcontrollers(8 位單片微控制器)
中文描述: 8位單片機微控制器(8位單片微控制器)
文件頁數(shù): 90/148頁
文件大小: 621K
代理商: ΜPD78F9217Y
Preliminary Product Information
90
μ
PD78F9217Y
(e) SMB input level setting register 0 (SMBVI0)
SMBVI0 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears SMBVI0 to 00H.
Figure 7-42. Format of SMB Input Level Setting Register 0
TOS02
0
TOS02
TOS01
TOS00
SVIN0
0
LVL01
LVL00
SMBVI0
Symbol
Address
When reset
R/W
FF7DH
00H
R/W
6
7
5
4
3
2
1
0
SVIN0
Input level selection bit
Same input level as the ordinary hysteresis
0
The voltage set with LVL01 and LVL00 is used as the SCL0 and SDA0 input level threshold.
1
LVL01
LVL00
Input level selection bits
Note
The input level is 0.1875
×
V
DD
.
The input level is 0.25
×
V
DD
.
The input level is 0.375
×
V
DD
.
The input level is 0.5
×
V
DD
.
0
0
1
1
0
1
0
1
TOS01
TOS00
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1,024/f
TO
(16.4 ms)
896/f
TO
(14.3 ms)
f
TO
= f
CC
/2
6
f
TO
= f
CC
/2
7
f
TO
= f
CC
/2
8
f
TO
= f
XT
768/f
TO
(12.3 ms)
640/f
TO
(10.2 ms)
512/f
TO
(8.19 ms)
384/f
TO
(6.14 ms)
256/f
TO
(4.10 ms)
128/f
TO
(2.05 ms)
1,024/f
TO
(32.8 ms)
896/f
TO
(28.7 ms)
768/f
TO
(24.6 ms)
640/f
TO
(20.5 ms)
512/f
TO
(16.4 ms)
384/f
TO
(12.3 ms)
256/f
TO
(8.19 ms)
128/f
TO
(4.10 ms)
1,024/f
TO
(65.5 ms)
896/f
TO
(57.3 ms)
768/f
TO
(49.2 ms)
640/f
TO
(41.0 ms)
512/f
TO
(32.8 ms)
384/f
TO
(24.6 ms)
256/f
TO
(16.4 ms)
128/f
TO
(8.19 ms)
1,024/f
TO
(31.3 ms)
896/f
TO
(27.3 ms)
768/f
TO
(23.4 ms)
640/f
TO
(19.5 ms)
512/f
TO
(15.6 ms)
384/f
TO
(11.7 ms)
256/f
TO
(7.8 ms)
128/f
TO
(3.9 ms)
Time-out time setting bits
Note
Set an input level from 0.75 to 1.25 V.
Caution
Bits 2 and 7 must be fixed to 0.
Remarks 1.
f
CC
: Main system clock oscillation frequency
2.
f
XT
: Subsystem clock oscillation frequency
3.
f
TO
: Clock selected using bits 0 and 1 (TOCL00, TOCL01) of SMB mode register 0 (SMBM0).
4.
The parenthesized values apply to operation at f
CC
= 4.0 MHz or f
XT
= 32.768 kHz.
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