參數(shù)資料
型號: μPD78F9217Y
廠商: NEC Corp.
英文描述: 8 Bit Single Chip Microcontrollers(8 位單片微控制器)
中文描述: 8位單片機微控制器(8位單片微控制器)
文件頁數(shù): 35/148頁
文件大?。?/td> 621K
代理商: ΜPD78F9217Y
Preliminary Product Information
35
μ
PD78F9217Y
7.2.3
Clock generator control registers
The clock generator is controlled using the following registers.
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
(1) Processor clock control register (PCC)
The PCC selects a CPU clock and specifies a corresponding frequency division ratio.
It is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input loads 02H into the PCC.
Figure 7-8. Format of Processor Clock Control Register
Control of main system clock oscillator operation
MCC
0
1
Operation enabled
Operation disabled
CPU clock (f
CPU
) selection
Note
CSS0
0
0
1
1
f
CC
f
CC
/2
2
f
XT
/2
PCC1
0
1
0
1
(0.25 s)
(1.0 s)
(61 s)
MCC
0
0
0
0
0
PCC1
0
PCC
Symbol
Address
When reset
R/W
FFFBH
02H
R/W
6
7
0
5
4
3
2
1
Note
A CPU clock is selected by a combination of the PCC1 flag in the processor clock control register (PCC)
and the CSS0 flag in the subclock control register (CSS). (See
(3)
in
Section 7.2.3
.)
Cautions 1. Bit 0 and bits 2 to 6 must be fixed to 0.
2. MCC can be set only when the subsystem clock is selected as the CPU clock.
3. Never set MCC when an external clock is applied. This is because the CL2 pin is pulled up to
V
DD0
or V
DD1
.
Remarks 1.
f
CC
: Main system clock oscillation frequency
2.
f
XT
: Subsystem clock oscillation frequency
3.
The parenthesized values apply to operation with f
CC
= 4.0 MHz or f
XT
= 32.768 kHz.
4.
Minimum instruction execution time: 2 f
CPU
f
CPU
= 0.25
μ
s : 0.5
μ
s
f
CPU
= 1.0
μ
s
: 2.0
μ
s
f
CPU
= 61
μ
s
: 122
μ
s
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