參數(shù)資料
型號(hào)： μPD78F4216Y
廠商： NEC Corp.
英文描述： 8/16 Bit RISC Microcontrollers(8/16位RISC微控制器)
中文描述： 8 / 16位RISC微控制器（8 / 16位的RISC微控制器）
文件頁(yè)數(shù)： 27/56頁(yè)
文件大?。?/td> 407K
代理商： ΜPD78F4216Y
μ
PD78F4216Y
27
Preliminary Data Sheet U11824EJ1V0DS00
AC Characteristics (T
A
= –10 to +60
°
C, V
DD
= AV
DD
= 2.7 to 5.5 V, V
SS
= AV
SS
= 0 V)
(1) Read/write operation (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Cycle time (Minimum Instruciton
execution time)
t
CYK
4.5 V
≤
V
DD
≤
5.5 V
80
ns
2.7 V
≤
V
DD
< 4.5 V
160
ns
Address setup time (to ASTB
↓
)
t
SAST
V
DD
= 5.0 V
(0.5 + a) T – 11
29
ns
V
DD
= 3.0 V
(0.5 + a) T – 15
65
ns
Address hold time (from ASTB
↓
) t
HSTLA
V
DD
= 5.0 V
0.5T – 19
21
ns
V
DD
= 3.0 V
0.5T – 24
56
ns
ASTB high-level width
t
WSTH
V
DD
= 5.0 V
(0.5 + a) T – 17
23
ns
V
DD
= 3.0 V
(0.5 + a) T – 40
40
ns
Address hold time (from RD
↑
)
t
HRA
V
DD
= 5.0 V
0.5T – 14
26
ns
V
DD
= 3.0 V
0.5T – 14
66
ns
RD
↓
delay time from address
t
DAR
V
DD
= 5.0 V
(1 + a) T – 24
56
ns
V
DD
= 3.0 V
(1 + a) T – 24
136
ns
Address float time (from RD
↓
)
t
FRA
0
ns
Data input time from address
t
DAID
V
DD
= 5.0 V
(2.5 + a + n) T – 37
403
ns
V
DD
= 3.0 V
(2.5 + a + n) T – 52
828
ns
Data input time from ASTB
↓
t
DSTID
V
DD
= 5.0 V
(2 + n) T – 35
285
ns
V
DD
= 3.0 V
(2 + n) T – 50
590
ns
Data input time from RD
↓
t
DRID
V
DD
= 5.0 V
(1.5 + n) T – 40
240
ns
V
DD
= 3.0 V
(1.5 + n) T – 50
510
ns
RD
↓
delay time from ASTB
↓
t
DSTR
V
DD
= 5.0 V
0.5T – 9
31
ns
V
DD
= 3.0 V
0.5T – 9
71
ns
Data hold time (from RD
↑
)
t
HRID
0
ns
Address active time from RD
↑
t
DRA
V
DD
= 5.0 V
0.5T – 2
38
ns
V
DD
= 3.0 V
0.5T – 12
68
ns
ASTB
↑
delay time from RD
↑
t
DRST
V
DD
= 5.0 V
0.5T – 9
31
ns
V
DD
= 3.0 V
0.5T – 9
71
ns
RD low-level width
t
WRL
V
DD
= 5.0 V
(1.5 + n) T – 25
95
ns
V
DD
= 3.0 V
(1.5 + n) T – 30
210
ns
WR
↓
delay time from address
t
DAW
V
DD
= 5.0 V
(1 + a) T – 24
56
ns
V
DD
= 3.0 V
(1 + a) T – 24
136
ns
Address hold time (from WR
↑
)
t
HWA
V
DD
= 5.0 V
0.5T – 14
26
ns
V
DD
= 3.0 V
0.5T – 14
66
ns
Data output delay time from
ASTB
↓
t
DSTOD
V
DD
= 5.0 V
0.5T + 15
55
ns
V
DD
= 3.0 V
0.5T + 20
100
ns
Remark
T: t
CYK
= 1/f
XX
(f
XX
: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n
≥
0)
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