26
LIST OF FIGURES (3/5)
Figure No.
Title
Page
9-8
9-9
9-10
9-11
9-12
9-13
9-14
External Event Counter Operation Timings (with Rising Edge Specified) ........................................
Square-wave Output Operation Timing ............................................................................................
PWM Output Operation Timing .........................................................................................................
Timing of Operation by Change of CR5n ..........................................................................................
16-Bit Resolution Cascade Connection Mode ..................................................................................
8-Bit Counters Start Timing...............................................................................................................
Timing after Compare Register Transition during Timer Count Operation ........................................
200
201
203
204
206
206
207
10-1
10-2
10-3
Watch Timer Block Diagram .............................................................................................................
Watch Timer Mode Control Register (WTM) Format ........................................................................
Operation Timing of Watch Timer/Interval Timer...............................................................................
209
211
213
11-1
11-2
11-3
11-4
Watchdog Timer Block Diagram .......................................................................................................
Watchdog Timer Clock Select Register (WDCS) Format..................................................................
Watchdog Timer Mode Register (WDTM) Format ............................................................................
Oscillation Stabilization Time Select Register (OSTS) Format .........................................................
215
218
219
220
12-1
12-2
12-3
12-4
Clock Output/Buzzer Output Control Circuit Block Diagram .............................................................
Clock Output Selection Register (CKS) Format................................................................................
Port Mode Register 7 (PM7) Format.................................................................................................
Remote Control Output Application Example ...................................................................................
223
225
226
227
13-1
13-2
13-3
13-4
8-bit A/D Converter Block Diagram ...................................................................................................
A/D Converter Mode Register (ADM0) Format .................................................................................
Analog Input Channel Specification Register (ADS0) Format ..........................................................
External Interrupt Rising Edge Enable Register (EGP), Internal Interrupt Falling Edge Enable
Register (EGN) Format .....................................................................................................................
Basic Operation of 8-Bit A/D Converter ............................................................................................
Relationship between Analog Input Voltage and A/D Conversion Result .........................................
A/D Conversion by Hardware Start (When Falling Edge is Specified) .............................................
A/D Conversion by Software Start ....................................................................................................
Example of Method of Reducing Current Dissipation in Standby Mode ...........................................
Analog Input Pin Connection ............................................................................................................
A/D Conversion End Interrupt Request Generation Timing ..............................................................
Serving AV
DD
Pins .............................................................................................................................
229
233
234
235
237
238
240
241
242
243
244
245
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
14-1
14-2
14-3
14-4
10-Bit A/D Converter Block Diagram ................................................................................................
A/D Converter Mode Register (ADM0) Format .................................................................................
Analog Input Channel Specification Register (ADS0) Format ..........................................................
External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable
Register (EGN) Format .....................................................................................................................
Basic Operation of 10-Bit A/D Converter ..........................................................................................
Relationship between Analog Input Voltage and A/D Conversion Result .........................................
A/D Conversion by Hardware Start (When Falling Edge is Specified) .............................................
A/D Conversion by Software Start ....................................................................................................
247
250
251
251
253
254
255
256
14-5
14-6
14-7
14-8