參數(shù)資料
型號(hào): μPD784031Y
廠商: NEC Corp.
英文描述: 8/16 Bit Single Chip Microcontrollers(8/16 位微控制器)
中文描述: 8 / 16位單片機(jī)微控制器(8 / 16位微控制器)
文件頁(yè)數(shù): 12/66頁(yè)
文件大小: 392K
代理商: ΜPD784031Y
μ
PD784031Y
12
5.2 Non-Port Pins
Pin Name
I/O
Alternate function
Function
TO0-TO3
Output
P34-P37
Timer output
CI
Input
P23/INTP2
Count clock input to timer/counter 2
RxD
Input
P30/SI1
Serial data input (UART0)
RxD2
P13/SI2
Serial data input (UART2)
TxD
Output
P31/SO1
Serial data output (UART0)
TxD2
P14/SO2
Serial data output (UART2)
ASCK
Input
P25/INTP4/SCK1
Baud rate clock input (UART0)
ASCK2
P12/SCK2
Baud rate clock input (UART2)
SDA
I/O
P33/SO0
Serial data input/output (2-wire serial I/O, I
2
C bus)
SI0
Input
P27
Serial data input (3-wire serial I/O0)
SI1
P30/RxD
Serial data input (3-wire serial I/O1)
SI2
P13/RxD2
Serial data input (3-wire serial I/O2)
SO0
Output
P33/SDA
Serial data output (3-wire serial I/O0)
SO1
P31/TxD
Serial data output (3-wire serial I/O1)
SO2
P14/TxD2
Serial data output (3-wire serial I/O2)
SCK0
I/O
P32/SCL
Serial clock input/output (3-wire serial I/O0)
SCK1
P25/INTP4/ASCK
Serial clock input/output (3-wire serial I/O1)
SCK2
P12/ASCK2
Serial clock input/output (3-wire serial I/O2)
SCL
P32/SCK0
Serial clock input/output (2-wire serial I/O, I
2
C bus)
NMI
Input
P20
External interrupt requests
INTP0
P21
Count clock input to timer/counter 1
Capture trigger signal of CR11 or CR12
INTP1
P22
Count clock input to timer/counter 2
Capture trigger signal of CR22
INTP2
P23/CI
Count clock input to timer/counter 2
Capture trigger signal of CR21
INTP3
P24
Count clock input to timer/counter 0
Capture trigger signal of CR02
INTP4
P25/ASCK/SCK1
INTP5
P26
Conversion start trigger input to A/D converter
AD0-AD7
I/O
Time-division address/data bus (for external memory connection)
A8-A15
Output
Higher address bus (for external memory connection)
A16-A19
Output
P60-P63
Higher address when address is extended (for external memory connection)
RD
Output
Read strobe to external memory
WR
Output
Write strobe to external memory
WAIT
Input
P66/HLDRQ
Wait insertion
REFRQ
Output
P67/HLDAK
Refresh pulse output to external pseudo static memory
HLDRQ
Input
P66/WAIT
Bus hold request input
HLDAK
Output
P67/REFRQ
Bus hold acknowledge output
ASTB
Output
Latch timing output of time-division address (A0 through A7)
(when accessing external memory)
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