
211
CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE
Figure 8-10. Format of Serial Bus Interface Control Register
(
μ
PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY
subseries,
μ
PD78070AY) (2/2)
R/W
ACKE
Controls automatic output of acknowledge signal
Note 1
0
Disables automatic output of acknowledge signal (output by ACKT is enabled).
Used for transmission or reception with 8-clock wait selected
Note 2
.
1
Enables automatic output of acknowledge signal.
Acknowledge signal is output in synchronization with falling edge of 9th clock of SCL (automatically
output when ACKE = 1). After output, this bit is not automatically cleared to 0.
Used for reception when 9-clock wait is selected.
R ACKD
Acknowledge detection
Clear condition (ACKD = 0)
Set condition (ACKD = 1)
On execution of transfer start instruction
When CSIE0 = 0
At RESET input
When acknowledge signal is detected at rising
edge of SCL clock after completion of transfer
R/W
Controls transmission N-ch open drain output in I
2
C bus mode
Note 4
0
Enables output (transmission)
1
Disables output (reception)
Notes 1.
Set this bit before starting transfer.
2.
Output the acknowledge signal on reception by using ACKT when 8-clock wait is selected.
3.
The wait status can be released by starting transfer of serial interface or receiving an address signal.
However, BSYE is not cleared to 0.
4.
Be sure to set BSYE to 1 when using the wake-up function.
Remark
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
BSYE
Note 3