
μ
PD78070AY
29
Interrupt
Type
Default
Note1
Priority
Interrupt Source
Internal/
External
Vector
Table
Address Type
Note2
Basic
Structure
Name
Trigger
Non-
maskable
—
INTWDT
Overflow of watchdog timer (When the watchdog timer
mode 1 is selected)
Internal
0004H
(A)
Maskable
0
INTWDT
Overflow of watchdog timer (When the interval timer
mode is selected)
(B)
1
INTP0
Pin input edge detection
External
0006H
(C)
2
INTP1
0008H
(D)
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTP6
0012H
8
INTCSI0
Completion of serial interface channel 0 transfer
Internal
0014H
(B)
9
INTCSI1
Completion of serial interface channel 1 transfer
0016H
10
INTSER
Occurrence of serial interface channel 2 UART reception error
0018H
11
INTSR
Completion of serial interface channel 2 UART reception
001AH
INTCSI2
Completion of serial interface channel 2 3-wire transfer
12
INTST
Completion of serial interface channel 2 UART transmission
001CH
13
INTTM3
Reference time interval signal from watch timer
001EH
14
INTTM00
Generation of matching signal of 16-bit timer register and
capture/compare register (CR00)
0020H
15
INTTM01
Generation of matching signal of 16-bit timer register and
capture/compare register (CR01)
0022H
16
INTTM1
Generation of matching signal of 8-bit timer/event counter 1
0024H
17
INTTM2
Generation of matching signal of 8-bit timer/event counter 2
0026H
18
INTAD
Completion of A/D conversion
0028H
19
INTTM5
Generation of matching signal of 8-bit timer/event counter 5
002AH
20
INTTM6
Generation of matching signal of 8-bit timer/event counter 6
002CH
Software
—
BRK
Execution of BRK instruction
—
003EH
(E)
Table 6-1. List of Interrupt Sources
Notes 1.
Default priority is the priority order when several maskable interrupt requests are generated at the same
time. 0 is the highest priority and 20 is the lowest priority.
2.
Basic structure types (A) to (E) correspond to (A) to (E) in Figure 6-1.