
11
CHAPTER 1 OVERVIEW
Table 1-3. Function Overview of the
μ
PD780208 Subseries (1/2)
Product name
μ
PD780204
μ
PD780205
μ
PD780206
μ
PD780208
μ
PD78P0208
Item
ROM
Masked ROM
One-time PROM/EPROM
32K bytes
40K bytes
48K bytes
60K bytes
60K bytes
Note 1
High-speed RAM
1024 bytes
Extended RAM
-
1024 bytes
1024 bytes
Note 2
Buffer RAM
64 bytes
FIP display RAM
80 bytes
General-purpose registers
8 bits x 8 x 4 banks
For main system clock
0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s/6.4
μ
s (at 5.0 MHz)
For subsystem clock
122
μ
s (at 32.768 kHz)
Instruction set
16-bit operations
Multiplication/division (8 bits x 8 bits, 16 bits/8 bits)
Bit (set, reset, test, Boolean operations)
BCD conversion, etc.
I/O ports (including those
Total
:
74 pins
multiplexed with FIP pins)
CMOS input
:
2 pins
CMOS I/O
:
27 pins
N-ch open-drain I/O
:
5 pins
P-ch open-drain I/O
:
24 pins
P-ch open-drain output :
16 pins
FIP controller/driver
Total
:
53 pins
Segments :
9 to 40 pins
Digits
:
2 to 16 pins
A/D converter
8-bit resolution x 8 channels
Power supply voltage: AV
DD
= 4.0 to 5.5 V
Serial interface
3-wire serial I/O, SBI, or 2-wire serial I/O mode selectable : 1 channel
3-wire mode (with automatic transmission/
reception function of up to 64 bytes)
: 1 channel
Timer
16-bit timer/event counter :
1 channel
8-bit timer/event counter :
2 channels
Watch timer
:
1 channel
Watchdog timer
:
1 channel
Timer outputs
3 (one for 14-bit PWM output)
Notes 1.
The memory size switching register (IMS) can be used to select 32K, 40K, 48K, or 60K bytes.
2.
The internal extended RAM size switching register (IXS) can be used to select either 0 or 1024
bytes.
Internal
memory
Minimum
instruction
execution time
*