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CHAPTER 8 SERIAL INTERFACE APPLICATION
Figure 8-7.
Format of the Serial Bus Interface Control Register (Only for the
μ
PD78044F and
μ
PD780208 Subseries) (1/2)
R/W
RELT
This is used to output the bus release signal.
The SO latch is set (1) by RELT = 1. After setting the SO latch, this bit is automatically cleared (0).
In addition, it is cleared (0) when CSIE0 = 0.
R/W
CMDT
This is used for command signal output.
The SO latch is cleared (0) by CMDT = 1. After clearing the SO latch, this bit is automatically cleared (0).
In addition, it is cleared (0) when CSIE0 = 0.
R
RELD
Bus release detection
Clearing conditions (RELD = 0)
Setting conditions (RELD = 1)
When a start transfer instruction is executed
When the values in SIO0 and SVA do not match while
receiving an address
When CSIE0 = 0
When RESET is input
When a bus release signal (REL) is detected
R
CMDD
Command detection
Clearing conditions (CMDD = 0)
Setting conditions (CMDD = 1)
When a start transfer instruction is executed
When a bus release signal (REL) is detected
When CSIE0 = 0
When RESET is input
When a command signal (CMD) is detected
R/W
ACKT
The acknowledge signal is output synchronized to the falling edge of the SCK0 clock immediately after the execution
of the instruction that is set (1). After the output, this bit is automatically cleared (0).
In addition, when starting the transfer in the serial interface and CSIE0 = 0, this bit is also cleared (0).
Note
Bits 2, 3, and 6 (RELD, CMDD, ACKD) are read-only.
Remark
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
7
BSYE
6
ACKD
5
ACKE
4
ACKT
3
CMDD
2
RELD
1
CMDT
0
RELT
Symbol
SBIC
Address
FF61H
At reset
00H
R/W
R/W
Note