
46
CHAPTER 4 INSTRUCTION SET
8-Bit Data
XCH
A,r
Note 3
1
4
–
A
r
Transfer
A,saddr
2
8
12
A
(saddr)
A,sfr
2
–
12
A
(sfr)
A,!addr16
3
16
20+2n+2m
A
(addr16)
A,[DE]
1
8
12+2n+2m
A
(DE)
A,[HL]
1
8
12+2n+2m
A
(HL)
A,[HL+byte]
2
16
20+2n+2m
A
(HL+byte)
A,[HL+B]
2
16
20+2n+2m
A
(HL+B)
A,[HL+C]
2
16
20+2n+2m
A
(HL+C)
16-Bit Data
MOVW
rp,#word
3
12
–
rp
←
word
Transfer
saddrp,#word
4
16
20
(saddrp)
←
word
sfrp,#word
4
–
20
sfrp
←
word
AX,saddrp
2
12
16
AX
←
(saddrp)
saddrp,AX
2
12
16
(saddrp)
←
AX
AX,sfrp
2
–
16
AX
←
sfrp
sfrp,AX
2
–
16
sfrp
←
AX
AX,rp
Note 4
1
8
–
A X
←
r p
rp,AX
Note 4
1
8
–
rp
←
AX
AX,!addr16
3
20
24+4n
AX
←
(addr16)
!addr16,AX
3
20
24+4m
(addr16)
←
AX
XCHW
AX,rp
Note 4
1
8
–
AX
rp
8-Bit
ADD
A,#byte
2
8
–
A, CY
←
A+byte
×
×
×
Operation
saddr,#byte
3
12
16
(saddr), CY
←
(saddr) + byte
×
×
×
A,r
Note 3
2
8
–
A,CY
←
A+r
×
×
×
r,A
2
8
–
r,CY
←
r+A
×
×
×
A,saddr
2
8
10
A,CY
←
A+(saddr)
×
×
×
A,!addr16
3
16
18+2n
A,CY
←
A+(addr16)
×
×
×
A,[HL]
1
8
10+2n
A,CY
←
A+(HL)
×
×
×
A,[HL+byte]
2
16
18+2n
A,CY
←
A+(HL+byte)
×
×
×
A,[HL+B]
2
16
18+2n
A, CY
←
A+(HL+B)
×
×
×
A,[HL+C]
2
16
18+2n
A,CY
←
A+(HL+C)
×
×
×
Notes 1.
When the internal high-speed RAM area is accessed or in the instruction with no data access.
When an area except the internal high-speed RAM area is accessed.
Except r = A.
Only when rp = BC, DE or HL.
2.
3.
4.
Remarks 1.
1 instruction clock cycle is 1 CPU clock cycle (f
CPU
) selected by the processor clock control register
(PCC).
Number of clock cycles is when there is a program in the internal ROM area.
n indicates the number of waits when the external memory expansion area is read.
m indicates the number of waits when the external memory expansion area is written to.
2.
3.
4.
Instruction
Group
Clock
Flag
Mnemonic
Operands
Byte
Operation
Note 1
Note 2
Z AC CY