212
CHAPTER 9 8-BIT TIMER/EVENT COUNTER
Table 9-6. Interval Time of 8-Bit Timer/Event Counter 1
TCL13
TCL12
TCL11
TCL10
Minimum Interval Time
Maximum Interval Time
Resolution
0
0
0
0
TI1 input cycle
2
8
×
TI1 input cycle
TI1 input edge cycle
0
0
0
1
TI1 input cycle
2
8
×
TI1 input cycle
TI1 input edge cycle
0
1
1
0
2
2
×
1/f
X
(400 ns)
2
10
×
1/f
X
(102.4
μ
s)
2
2
×
1/f
X
(400 ns)
0
1
1
1
2
3
×
1/f
X
(800 ns)
2
11
×
1/f
X
(204.8
μ
s)
2
3
×
1/f
X
(800 ns)
1
0
0
0
2
4
×
1/f
X
(1.6
μ
s)
2
12
×
1/f
X
(409.6
μ
s)
2
4
×
1/f
X
(1.6
μ
s)
1
0
0
1
2
5
×
1/f
X
(3.2
μ
s)
2
13
×
1/f
X
(819.2
μ
s)
2
5
×
1/f
X
(3.2
μ
s)
1
0
1
0
2
6
×
1/f
X
(6.4
μ
s)
2
14
×
1/f
X
(1.64 ms)
2
6
×
1/f
X
(6.4
μ
s)
1
0
1
1
2
7
×
1/f
X
(12.8
μ
s)
2
15
×
1/f
X
(3.28 ms)
2
7
×
1/f
X
(12.8
μ
s)
1
1
0
0
2
8
×
1/f
X
(25.6
μ
s)
2
16
×
1/f
X
(6.55 ms)
2
8
×
1/f
X
(25.6
μ
s)
1
1
0
1
2
9
×
1/f
X
(51.2
μ
s)
2
17
×
1/f
X
(13.1 ms)
2
9
×
1/f
X
(51.2
μ
s)
1
1
1
0
2
10
×
1/f
X
(102.4
μ
s)
2
18
×
1/f
X
(26.2 ms)
2
10
×
1/f
X
(102.4
μ
s)
1
1
1
1
2
12
×
1/f
X
(409.6
μ
s)
2
20
×
1/f
X
(104.9 ms)
2
12
×
1/f
X
(409.6
μ
s)
Setting prohibited
Remarks
1.
f
X
2.
TCL10-TCL13: Bits 0 through 3 of timer clock select register 1 (TCL1)
3.
( )
: At f
X
= 10.0 MHz operation
: Main system clock oscillation frequency
Table 9-7. Interval Time of 8-Bit Timer/Event Counter 2
TCL17
TCL16
TCL15
TCL14
Minimum Interval Time
Maximum Interval Time
Resolution
0
0
0
0
TI2 input cycle
2
8
×
TI2 input cycle
TI2 input edge cycle
0
0
0
1
TI2 input cycle
2
8
×
TI2 input cycle
TI2 input edge cycle
0
1
1
0
2
2
×
1/f
X
(400 ns)
2
10
×
1/f
X
(102.4
μ
s)
2
2
×
1/f
X
(400 ns)
0
1
1
1
2
3
×
1/f
X
(800 ns)
2
11
×
1/f
X
(204.8
μ
s)
2
3
×
1/f
X
(800 ns)
1
0
0
0
2
4
×
1/f
X
(1.6
μ
s)
2
12
×
1/f
X
(409.6
μ
s)
2
4
×
1/f
X
(1.6
μ
s)
1
0
0
1
2
5
×
1/f
X
(3.2
μ
s)
2
13
×
1/f
X
(819.2
μ
s)
2
5
×
1/f
X
(3.2
μ
s)
1
0
1
0
2
6
×
1/f
X
(6.4
μ
s)
2
14
×
1/f
X
(1.64 ms)
2
6
×
1/f
X
(6.4
μ
s)
1
0
1
1
2
7
×
1/f
X
(12.8
μ
s)
2
15
×
1/f
X
(3.28 ms)
2
7
×
1/f
X
(12.8
μ
s)
1
1
0
0
2
8
×
1/f
X
(25.6
μ
s)
2
16
×
1/f
X
(6.55 ms)
2
8
×
1/f
X
(25.6
μ
s)
1
1
0
1
2
9
×
1/f
X
(51.2
μ
s)
2
17
×
1/f
X
(13.1 ms)
2
9
×
1/f
X
(51.2
μ
s)
1
1
1
0
2
10
×
1/f
X
(102.4
μ
s)
2
18
×
1/f
X
(26.2 ms)
2
10
×
1/f
X
(102.4
μ
s)
1
1
1
1
2
12
×
1/f
X
(409.6
μ
s)
2
20
×
1/f
X
(104.9 ms)
2
12
×
1/f
X
(409.6
μ
s)
Setting prohibited
Remarks
1.
f
X
2.
TCL14-TCL17: Bits 4 through 7 of timer clock select register 1 (TCL1)
3.
( )
: At f
X
= 10.0 MHz operation
: Main system clock oscillation frequency
Others
Others