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CHAPTER 7 CLOCK GENERATION CIRCUIT
7.5 Operation of Clock Generation Circuit
The clock generation circuit generates the following clocks and control the operation modes of the CPU, such as
the standby mode:
Main system clock f
X
Subsystem clock f
XT
CPU clock f
CPU
Clock to peripheral hardware
The operation of the clock generation circuit is determined by the processor clock control register (PCC), as follows:
(a) The slowest mode (6.4
μ
s: at 10.0 MHz operation) of the main system clock is selected when the RESET signal
is generated (PCC = 04H). While a low level is input to the RESET pin, oscillation of the main system clock
is stopped.
(b) Five types of CPU clocks (0.4
μ
s, 0.8
μ
s, 1.6
μ
s, 3.2
μ
s, and 6.4
μ
s: at 10.0 MHz operation) can be selected
by the PCC setting with the main system clock selected.
(c) Two standby modes, STOP and HALT, can be used when the main system clock is selected. In a system
where the subsystem clock is not used, the current consumption in the STOP mode can be further reduced
by specifying not to use the internal feedback resistor by using the bit 6 (FRC) of PCC.
(d) The subsystem clock can be selected by PCC and the microcomputer can operate with a low current
consumption (122
μ
s: at 32.768 kHz operation).
(e) Oscillation of the main system clock can be stopped by PCC with the subsystem clock selected. Moreover,
the HALT mode can be used. However, the STOP mode cannot be used (oscillation of the subsystem clock
cannot be stopped).
(f)
The clock to the peripheral hardware is supplied by dividing the main system clock. However, the subsystem
clock is supplied to the watch timer and clock output function only. Therefore, the watch function and clock
output function can be continuously used even in the standby status. The other peripheral hardware is stopped
when the main system clock is stopped because the peripheral hardware operates on the main system clock
(except, however, the external clock input operation).