參數(shù)資料
型號: μPD75P3116
廠商: NEC Corp.
英文描述: 4 Bit Single Chip Microcontrollers(4位單片微控制器)
中文描述: 4位單片微控制器(4位單片微控制器)
文件頁數(shù): 38/60頁
文件大小: 350K
代理商: ΜPD75P3116
38
μ
PD75P3116
SBI Mode (SCK...Internal clock output (master)): (T
A
= –40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY3
V
DD
= 2.7 to 5.5 V
1300
ns
3800
ns
SCK high-/low-level
t
KL3
,
t
KH3
V
DD
= 2.7 to 5.5 V
t
KCY3
/2–50
ns
width
t
KCY3
/2–150
ns
SB0, 1 setup time
t
SIK3
V
DD
= 2.7 to 5.5 V
150
ns
(to SCK
)
500
ns
SB0, 1 hold time (from SCK
)
t
KSI3
t
KCY3
/2
ns
SCK
↓→
SB0, 1
t
KSO3
R
L
= 1 k
,
V
DD
= 2.7 to 5.5 V
0
250
ns
output delay time
C
L
= 100 pF
Note
0
1000
ns
SCK
↑→
SB0, 1
t
KSB
t
KCY3
ns
SB0, 1
↓→
SCK
t
SBK
t
KCY3
ns
SB0, 1 low-level width
t
SBL
t
KCY3
ns
SB0, 1 high-level width
t
SBH
t
KCY3
ns
Note
R
L
and C
L
are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
SBI Mode (SCK...External clock input (slave)): (T
A
= –40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY4
V
DD
= 2.7 to 5.5 V
800
ns
3200
ns
SCK high-/low-level
t
KL4
,
t
KH4
V
DD
= 2.7 to 5.5 V
400
ns
width
1600
ns
SB0, 1 setup time
t
SIK4
V
DD
= 2.7 to 5.5 V
100
ns
(to SCK
)
150
ns
SB0, 1 hold time (from SCK
)
t
KSI4
t
KCY4
/2
ns
SCK
↓→
SB0, 1 output
t
KSO4
R
L
= 1 k
,
V
DD
= 2.7 to 5.5 V
0
300
ns
delay time
C
L
= 100 pF
Note
0
1000
ns
SCK
↑→
SB0, 1
t
KSB
t
KCY4
ns
SB0, 1
↓→
SCK
t
SBK
t
KCY4
ns
SB0, 1 low-level width
t
SBL
t
KCY4
ns
SB0, 1 high-level width
t
SBH
t
KCY4
ns
Note
R
L
and C
L
are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
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