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19
LIST OF FIGURES (4/4)
Figure No.
Title
Page
5-107
5-108
5-109
5-110
5-111
5-112
5-113
5-114
5-115
5-116
5-117
5-118
5-119
5-120
5-121
5-122
LCD Drive Power Connection Examples (when split resistor is incorporated)................................... 277
LCD Drive Power Supply Connection Examples................................................................................ 278
Static Mode LCD Display Pattern and Electrode Connection ............................................................ 279
Static LCD Panel Connection Example.............................................................................................. 280
Static LCD Drive Waveform Example................................................................................................. 281
Division by 2 Mode LCD Display Pattern and Electrode Connection ................................................. 282
Division by 2 LCD Panel Connection Example .................................................................................. 283
Division by 2 LCD Drive Waveform Example (1/2 bias method) ........................................................ 284
Division by 3 Mode LCD Display Pattern and Electrode Connection ................................................. 285
Division by 3 LCD Panel Connection Example .................................................................................. 286
Division by 3 LCD Drive Waveform Example (1/2 bias method) ........................................................ 287
Division by 3 LCD Drive Waveform Example (1/3 bias method) ........................................................ 288
Division by 4 Mode LCD Display Pattern and Electrode Connection ................................................. 289
Division by 4 LCD Panel Connection Example .................................................................................. 290
Division by 4 LCD Drive Waveform Example (1/3 bias method) ........................................................ 291
Bit Sequential Buffer Format .............................................................................................................. 292
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
Interrupt Control Circuit Block Diagram.............................................................................................. 296
Interrupt Vector Table ......................................................................................................................... 298
Interrupt Priority Selection Register ................................................................................................... 301
Configurations of INT0, and INT4 ...................................................................................................... 303
Noise Detection Circuit Input/Output Timing ...................................................................................... 304
INT0 Edge Detection Mode Register (IM0) Format............................................................................ 305
Interrupt Processing Sequence.......................................................................................................... 307
Nestings by High-Order Priority Interrupts ......................................................................................... 308
Nestings by Changing Interrupt Status Flag ...................................................................................... 309
KR0-KR3 Block Diagram.................................................................................................................... 324
Format of INT2 Edge Detection Mode Register (IM2)........................................................................ 347
7-1
7-2
Standby Mode Release Operation ..................................................................................................... 332
Wait Time When STOP Mode Is Released ........................................................................................ 333
8-1
8-2
Configuration of Reset Function......................................................................................................... 337
Reset Operation by RESET Signal Generation ................................................................................. 337