參數(shù)資料
型號(hào): μPD70P3002
廠商: NEC Corp.
英文描述: 16/32 Single -Chip Microcontroller(16/32 位單片微控制器)
中文描述: 16/32單片機(jī)(16/32位單片微控制器)
文件頁(yè)數(shù): 15/56頁(yè)
文件大小: 367K
代理商: ΜPD70P3002
μ
PD70P3002
15
(1) Page data latch mode
The page data latch mode can be set by making the CE and PGM pins high and OE pin low at the beginning
of the page write mode.
In the page data latch mode, 1 page or 4 bytes of data are latched to the internal address/data latch circuit.
(2) Page write mode
In this mode, page write is executed by applying a program pulse of 0.1 ms to the PGM pin when CE = H and
OE = H after 1 page or 4 bytes of addresses and data have been latched in the page data latch mode. After
that, the program is verified when CE = L and OE = L.
If the program cannot be written by applying the program pulse once, writing and verification are repeatedly
executed X times (X
10).
(3) Byte write mode
Byte write is executed by applying a program pulse (active low) of 0.1 ms to the PGM pin when CE = L and OE
= H. After that, the program is verified when OE = L.
If the program cannot be written by applying the program pulse once, writing and verification are repeatedly
executed X times (X
10).
(4) Program verify mode
The program verify mode is set when CE = L, OE = L, and PGM = H.
Check to see if the program has been correctly written, in this mode.
(5) Program inhibit mode
The program inhibit mode is used to write a program to one of several
μ
PD70P3002s whose OE, V
PP
and D0
through D7 pins are connected in parallel.
To write a program, either the page write mode or byte write mode above is used. At this time, the program is
not written to any device whose PGM pin is made high.
(6) Read mode
The read mode is set when CE = L, OE = L, and PGM = H.
(7) Output disable mode
The data output goes into a high-impedance state and the output disable mode is set by making CE low and
OE high.
When two or more
μ
PD70P3002s are connected to the data bus, any one of the devices can be selected and
data can be read by controlling the OE pin.
(8) Standby mode
The standby mode is set by making CE high.
In this mode, the data output goes into a high-impedance state regardless of the status of OE.
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