參數(shù)資料
型號(hào): μPD70F3008
廠商: NEC Corp.
英文描述: 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器)
中文描述: 16/32位單片機(jī)微控制器(16/32位單片微控制器)
文件頁數(shù): 21/141頁
文件大?。?/td> 374K
代理商: ΜPD70F3008
9
CHAPTER 2 REGISTER SET
2.2.2 NMI status saving registers
The V850 family is provided with two NMI status saving registers: FEPC and FEPSW.
The contents of the PC and PSW are respectively saved in these registers when an NMI occurs.
The value saved to the FEPC is, like the EIPC, the address of the instruction next to the one executed when the
NMI has occurred (if the NMI occurs while a division (DIVH) instruction is executed, the address of the division
instruction under execution is saved).
The current value of the PSW is saved to the FEPSW.
Bits 24 through 31 of the FEPC and bits 8 through 31 of the FEPSW are fixed to 0.
2.2.3 Exception cause register
The exception cause register (ECR) holds the cause information of an exception, maskable interrupt, or NMI when
any of these events occur. The ECR holds a code which identifies each interrupt source.
This is a read-only register, and therefore, no data can be written to it by using the LDSR instruction.
Bit Position
Field
Function
31 - 16
FECC
Fatal Error Cause Code
NMI code
15 - 0
EICC
Exception/Interrupt Cause Code
Exception/interrupt code
2.2.4 Program status word
The program status word is a collection of flags that indicate the status of the program (result of instruction
execution) and the status of the CPU. If the contents of the PSW register are modified by the LDSR instruction, the
PSW will assume the new value immediately after the LDSR instruction has been executed. In setting the ID flag
to 1, however, interrupts are already disabled even while the LDSR instruction is executing.
31
ECR
FECC
0
EICC
16 15
31
PSW
RFU
0
1
2
O
V
3
C
Y
4
S
A
T
5
I
D
6
E
P
7
N
P
S
Z
8
31
FEPC
PC
0
31
FEPSW
PSW
0
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