參數(shù)資料
型號: μPD703008
廠商: NEC Corp.
英文描述: 16/32 Bit RISC Microcontrollers(16/32位RISC微控制器)
中文描述: 16/32位RISC微控制器(16/32位的RISC微控制器)
文件頁數(shù): 79/141頁
文件大小: 374K
代理商: ΜPD703008
67
CHAPTER 5 INSTRUCTION
SATADD
Saturated Add
Instruction format
(1) SATADD reg1, reg2
(2) SATADD imm5, reg2
Operation
(1) GR [reg2]
saturated (GR [reg2] + GR [reg1])
(2) GR [reg2]
saturated (GR [reg2] + sign-extend (imm5))
Format
(1) Format I
(2) Format II
Op code
15
0
(1)
rrrrr000110RRRRR
15
0
(2)
rrrrr010001iiiii
Flag
CY
OV
S
Z
SAT
1 if a carry occurs from MSB; otherwise, 0.
1 if Overflow occurs; otherwise, 0.
1 if the result of the saturated operation is negative; otherwise, 0.
1 if the result of the saturated operation is 0; otherwise, 0.
1 if OV = 1; otherwise, not affected.
Instruction
(1) SATADD Saturated add register
(2) SATADD Saturated add Immediate (5-bit)
Explanation
(1) Adds the word data of general register reg1 to the word data of general register reg2, and
stores the result to general register reg2. However, if the result exceeds the maximum
positive value 7FFFFFFFH, 7FFFFFFFH is stored to reg2; if the result exceeds the
maximum negative value 80000000H, 80000000H is stored to reg2. The SAT flag is set
to 1. The data of general register reg1 is not affected.
(2) Adds a 5-bit immediate data, sign-extended to word length, to the word data of general
register reg2, and stores the result to general register reg2. However, if the result exceeds
the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored to reg2; if the result
exceeds the maximum negative value 80000000H, 80000000H is stored to reg2. The SAT
flag is set to 1.
Remark
The SAT flag is a cumulative flag. Once the result of the saturated operation instruction has
been saturated, this flag is set to 1 and is not reset to 0 even if the result of the subsequent
operation is not saturated.
Even if the SAT flag is set to 1, the saturated operation instruction is executed normally.
Caution
To reset the SAT flag to 0, load data to the PSW by using the LDSR instruction.
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