參數(shù)資料
型號: μPD703008
廠商: NEC Corp.
英文描述: 16/32 Bit RISC Microcontrollers(16/32位RISC微控制器)
中文描述: 16/32位RISC微控制器(16/32位的RISC微控制器)
文件頁數(shù): 116/141頁
文件大?。?/td> 374K
代理商: ΜPD703008
CHAPTER 8 PIPELINE
104
8.2 Pipeline Flow During Execution of Instructions
This section explains the pipeline flow during the execution of instructions.
During instruction fetch (IF stage) and memory access (MEM stage), the internal ROM/PROM and the internal RAM
are accessed, respectively. In this case, the IF and MEM stages are processed in 1 clock. In all other cases, the
required time for access consists of the fixed access time, with the addition in some cases of the path wait time. Access
times are shown in Figure 8-2 below.
Figure 8-2. Access Times (in clocks)
Resource (bus width)
Internal ROM/PROM
(32 bits)
Internal RAM
(32 bits)
Internal peripheral I/O
(8/16 bits)
External memory
(16 bits)
Stage
Instruction fetch
1
3
Not possible
3 + n
Memory access (MEM)
3
1
3 + n
3 + n
Remark
n: Wait number
8.2.1 Load instructions
[Instructions]
LD, SLD
[Pipeline]
[Description]
The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. If an instruction using the execution
result is placed immediately after the load instruction, data wait time occurs. For details, see
8.3 Pipeline Disorder
.
8.2.2 Store instructions
[Instructions]
ST, SST
[Pipeline]
[Description]
The pipeline consists of 5 stages, IF, ID, EX, MEM and WB. However, no operation is performed
in the WB stage, because no data is written to registers.
8.2.3 Arithmetic operation instructions (excluding multiply and divide instructions)
[Instructions]
MOV, MOVEA, MOVHI, ADD, ADDI, CMP, SUB, SUBR, SETF
[Pipeline]
[Description]
The pipeline consists of 5 stages, IF, ID, EX, MEM and WB. However, no operation is performed
in the MEM stage, because memory is not accessed.
IF
ID
IF
EX
ID
MEM
EX
WB
MEM
WB
Load instruction
Next instruction
1
2
3
4
5
6
Store instruction
Next instruction
IF
ID
IF
EX
ID
MEM
EX
WB
MEM
WB
1
2
3
4
5
6
IF
ID
IF
EX
ID
MEM
EX
WB
MEM
WB
Arithmetic operation
instruction
Next instruction
1
2
3
4
5
6
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