參數(shù)資料
型號: μPD4564841
廠商: NEC Corp.
英文描述: 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
中文描述: 6400位同步DRAM(6400同步動態(tài)RAM)的
文件頁數(shù): 25/84頁
文件大?。?/td> 697K
代理商: ΜPD4564841
25
μ
PD4564441, 4564841, 4564163 for Rev. E
9. Precharge
The precharge command can be issued anytime after t
RAS (MIN.)
is satisfied.
Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters
the idle state after t
RP
is satisfied. The parameter t
RP
is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is
as follows.
It is depending on the /CAS latency and clock cycle time.
In order to write all data to the memory cell correctly, the asynchronous parameter “t
DPL
” must be satisfied. The
t
DPL (MIN.)
specification defines the earliest time that a precharge command can be issued. Minimum number of clocks
is calculated by dividing t
DPL (MIN.)
with clock cycle time.
In summary, the precharge command can be issued relative to reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
/CAS latency
Read
Write
2
–1
+t
DPL (MIN.)
3
–2
+t
DPL (MIN.)
T0
T1
T2
T3
T4
T5
T6
T7
Burst length=4
Read
Read
Q1
Q2
Q3
Q4
PRE
Hi-Z
Q1
Q2
Q3
Q4
PRE
Hi-Z
(t
RAS
must be satisfied)
CLK
Command
/CAS latency = 2
DQ
Command
/CAS latency = 3
DQ
T8
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