參數(shù)資料
型號(hào)： μPD45256441
廠商： NEC Corp.
英文描述： 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
中文描述： 256M位同步DRAM（256M同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 9/84頁(yè)
文件大?。?/td> 1052K
代理商： ΜPD45256441
9
μ
PD45256441,45256841,45256163
Preliminary Data Sheet
13. Electrical Specifications (Preliminary) ...............................................................................34
13.1 AC Parameters for Read Timing......................................................................................39
13.2 AC Parameters for Write Timing......................................................................................41
13.3 Relationship between Frequency and Latency..............................................................42
13.4 Mode Register Write .........................................................................................................43
13.5 Power on Sequence & Auto Refresh...............................................................................44
13.6 /CS Function......................................................................................................................45
13.7 Clock Suspention during Burst Read (using CKE Function)........................................46
13.8 Clock Suspention during Burst Write (using CKE Function)........................................48
13.9 Power Down Mode and Clock Mask................................................................................50
13.10 CBR Refresh ......................................................................................................................51
13.11 Self Refresh (entry and exit).............................................................................................52
13.12 Random Column Read (Page with same bank) ..............................................................53
13.13 Random Column Write (Page with same bank) ..............................................................55
13.14 Random Row Read (Ping-Pong banks) ...........................................................................57
13.15 Random Row Write (Ping-Pong banks)...........................................................................59
13.16 Read and Write ..................................................................................................................61
13.17 Interleaved Column Read Cycle.......................................................................................63
13.18 Interleaved Column Write Cycle.......................................................................................65
13.19 Auto Precharge after Read Burst.....................................................................................67
13.20 Auto Precharge after Write Burst.....................................................................................69
13.21 Full Page Read Cycle ........................................................................................................71
13.22 Full Page Write Cycle........................................................................................................73
13.23 Byte Write Operation.........................................................................................................75
13.24 Burst Read and Single Write (Option) .............................................................................76
13.25 Full Page Random Column Read.....................................................................................77
13.26 Full Page Random Column Write.....................................................................................78
13.27 PRE (Precharge) Termination of Burst............................................................................79
14. Package Drawing..................................................................................................................81
15. Recommended Soldering Conditions ................................................................................82
相關(guān)PDF資料
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μPD45256841 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
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