參數(shù)資料
型號: μPD45256441
廠商: NEC Corp.
英文描述: 256M-Bit Synchronous DRAM(256M 同步 動態(tài)RAM)
中文描述: 256M位同步DRAM(256M同步動態(tài)RAM)的
文件頁數(shù): 11/84頁
文件大小: 1052K
代理商: ΜPD45256441
11
μ
PD45256441,45256841,45256163
Preliminary Data Sheet
2. Commands
Mode register set command
(/CS, /RAS, /CAS, /WE = Low)
The
μ
PD45256xxx has a mode register that defines how the device
operates. In this command, A0 through A12, BA0 and BA1 are the data
input pins. After power on, the mode register set command must be
executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2
CLK (t
RSC
) following this command, the
μ
PD45256xxx cannot
accept any other commands.
Activate command
(/CS, /RAS = Low, /CAS, /WE = High)
The
μ
PD45256xxx has four banks, each with 8,192 rows.
This command activates the bank selected by BA0 and BA1 and a row
address selected by A0 through A12.
This command corresponds to a conventional DRAM’s /RAS falling.
Precharge command
(/CS, /RAS, /WE = Low, /CAS = High)
This command begins precharge operation of the bank selected by BA0
and BA1. When A10 is High, all banks are precharged, regardless of BA0
and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is
precharged.
After this command, the
μ
PD45256xxx can’t accept the activate
command to the precharging bank during t
RP
(precharge to activate
command period).
This command corresponds to a conventional DRAM’s /RAS rising.
Fig.1 Mode register set
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
(Bank select)
Fig.2 Row address strobe and
bank activate command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Row
Row
Fig.3 Precharge command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
(Precharge select)
相關(guān)PDF資料
PDF描述
μPD45256841 256M-Bit Synchronous DRAM(256M 同步 動態(tài)RAM)
μPD4564163 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
μPD4564441 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
μPD4564841 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
μPD4564323 64M-bit Synchronous DRAM(64M 同步動態(tài)RAM)
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