參數(shù)資料
型號(hào): μPD43256B-X
廠商: NEC Corp.
英文描述: 256K-Bit CMOS Static RAM(256K CMOS 靜態(tài)RAM)
中文描述: 256K位CMOS靜態(tài)RAM(256K的CMOS靜態(tài)RAM)的
文件頁(yè)數(shù): 12/20頁(yè)
文件大?。?/td> 139K
代理商: ΜPD43256B-X
12
μ
PD43256B-X
Write Cycle Timing Chart 1 (WE Controlled)
t
WC
t
CW
t
AW
t
WP
t
AS
t
WR
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out
High
impe-
dance
High
impe-
dance
Data in
Indefinite data out
Address (Input)
CS (Input)
WE (Input)
I/O (Input/Output)
Cautions 1. CS or WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite
in phase with output signals.
Remarks 1.
Write operation is done during the overlap time of a low level CS and a low level WE.
2.
When WE is at low level, the I/O pins are always high impedance. When WE is at high level,
read operation is executed. Therefore OE should be at high level to make the I/O pins high
impedance.
3.
If CS changes to low level at the same time or after the change of WE to low level, the I/O pins
will remain high impedance state.
Write Cycle (3/3)
V
CC
2.7 V
Parameter
Symbol
μ
PD43256B-B10X
μ
PD43256B-B12X
μ
PD43256B-B15X
Unit
Condition
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
100
120
150
ns
CS to end of write
t
CW
70
90
100
ns
Address valid to end of write
t
AW
70
90
100
ns
Write pulse width
t
WP
60
80
90
ns
Data valid to end of write
t
DW
60
70
80
ns
Data hold time
t
DH
5
5
5
ns
Address setup time
t
AS
0
0
0
ns
Write recovery time
t
WR
0
0
0
ns
WE to output in high impedance
t
WHZ
35
40
40
ns
Note
Output active from end of write
t
OW
5
5
5
ns
Note
Loading condition is 1TTL + 50 pF.
相關(guān)PDF資料
PDF描述
μPD43256B 256K-Bit CMOS Static RAM(256K CMOS 靜態(tài)存儲(chǔ)器)
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