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參數資料
| 型號： | μPD4264400 |
| 廠商： | NEC Corp. |
| 英文描述： | 64 M-Bit Dynamic RAM(64M 動態(tài)RAM) |
| 中文描述： | 64 m位動態(tài)隨機存儲器（RAM的6400動態(tài)） |
| 文件頁數： | 11/28頁 |
| 文件大?。?/td> | 256K |
| 代理商： | ΜPD4264400 |
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μ
PD4264400, 4265400
11
Write Cycle
Parameter
Symbol
t
RAC
= 50 ns
t
RAC
= 60 ns
Unit
Notes
MIN.
MAX.
MIN.
MAX.
WE hold time referenced to CAS
t
WCH
8
–
10
–
ns
1
WE pulse width
t
WP
8
–
10
–
ns
1
WE lead time referenced to RAS
t
RWL
13
–
15
–
ns
WE lead time referenced to CAS
t
CWL
13
–
15
–
ns
WE setup time
t
WCS
0
–
0
–
ns
2
OE hold time
t
OEH
0
–
0
–
ns
Data-in setup time
t
DS
0
–
0
–
ns
3
Data-in hold time
t
DH
10
–
10
–
ns
3
Notes 1.
t
WP (MIN.)
is applied to late write cycles or read modify write cycles. In early write cycles, t
WCH (MIN.)
should
be met.
2.
If t
WCS
≥
t
WCS (MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3.
t
DS (MIN.)
and t
DH (MIN.)
are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
Parameter
Symbol
t
RAC
= 50 ns
t
RAC
= 60 ns
Unit
Note
MIN.
MAX.
MIN.
MAX.
Read modify write cycle time
t
RWC
128
–
153
–
ns
RAS to WE delay time
t
RWD
70
–
83
–
ns
1
CAS to WE delay time
t
CWD
33
–
38
–
ns
1
Column address to WE delay time
t
AWD
45
–
53
–
ns
1
Note 1.
If t
WCS
≥
t
WCS (MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If t
RWD
≥
t
RWD (MIN.)
, t
CWD
≥
t
CWD (MIN.)
, t
AWD
≥
t
AWD (MIN.)
and t
CPWD
≥
t
CPWD (MIN.)
, the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
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