參數(shù)資料
型號(hào): μPD30181
廠商: NEC Corp.
英文描述: 64-Bit RISC Microprosessor(64位RISC微處理器)
中文描述: 64位RISC Microprosessor(64位的RISC微處理器)
文件頁數(shù): 17/68頁
文件大?。?/td> 270K
代理商: ΜPD30181
17
μ
PD30700,30700L,30710
2. CPU INTERNAL ARCHITECTURE
2.1 Pipeline
2.1.1 Configuration
The V
R
10000 has a 5-way super scalar pipeline as illustrated below. This pipeline can simultaneously fetch and
decode four instructions in 1 Pcycle.
(1) FP addition pipeline
(2) FP multiplication pipeline
(3) Integer ALU1 pipeline
(4) Integer ALU2 pipeline
(5) Load/store pipeline
Figure 2-1. Pipeline
5-instruction
parallel execution
pipeline
FP addition pipeline
(FP queue)
Issue
RF
FAdd-1
FAdd-2
Issue
RF
FMpy-1
FMpy-2
FAdd-3
FMpy-3
Result
Stage 3
Issue
Stage 2
Decode
Stage 1
Fetch
Stage 4
Execute
Stage 5
Execute
Stage 6
Execute
Stage 7
Store
Result
Issue
RF
ALU1
Result
Issue
RF
ALU2
Result
Issue
RF
Addr.Calc
Data Cache
TLB
Queue
Branch address
Instruction fetch, decode (4 instructions/1 cycle)
Instruction execution
Primary
instruction
cache
Instruction
decode
Branch
unit
Integer register operand
FP queue,
FP register
Result
FP multiplication pipeline
(FP queue)
Integer ALU1 pipeline
(integer queue)
Integer ALU2 pipeline
(integer queue)
Load/store pipeline
(address queue)
7 pipeline stages
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μPD30700L 64-Bit Microprocessor(64位RISC微處理器)
μPD30700 64-Bit Microprocessor(64位RISC微處理器)
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