參數(shù)資料
型號(hào)： μPD30181
廠商： NEC Corp.
英文描述： 64-Bit RISC Microprosessor(64位RISC微處理器)
中文描述： 64位RISC Microprosessor（64位的RISC微處理器）
文件頁數(shù)： 11/68頁
文件大?。?/td> 270K
代理商： ΜPD30181
11
μ
PD30700,30700L,30710
TABLE OF CONTENTS
1.
PIN FUNCTIONS ...........................................................................................................................
1.1
Pin Function List.................................................................................................................
1.2
Recommended Connection of Unused Pins ...................................................................
13
13
16
2.
CPU INTERNAL ARCHITECTURE ..............................................................................................
2.1
Pipeline .................................................................................................................................
2.1.1
Configuration .............................................................................................................................
2.1.2
Operation ...................................................................................................................................
2.2
CPU Registers (virtual registers)......................................................................................
2.3
System Control Coprocessor (CP0) .................................................................................
2.3.1
CP0 registers .............................................................................................................................
2.4
Data Format and Addressing ............................................................................................
2.5
Virtual Storage.....................................................................................................................
2.5.1
Virtual address space................................................................................................................
2.5.2
Address translation ...................................................................................................................
2.6
Cache ....................................................................................................................................
2.6.1
Primary cache............................................................................................................................
2.6.2
Secondary cache.......................................................................................................................
17
17
17
18
19
20
20
22
24
24
27
29
29
29
3.
FPU INTERNAL ARCHITECTURE...............................................................................................
3.1
Internal Function Block......................................................................................................
3.2
FPU Registers......................................................................................................................
3.3
Data Format .........................................................................................................................
30
30
30
31
4.
INTERFACE ...................................................................................................................................
4.1
System Interface .................................................................................................................
4.1.1
Setting operating frequency of system interface .....................................................................
4.2
Secondary Cache Interface ...............................................................................................
4.3
Clock Interface ....................................................................................................................
4.3.1
System interface clock and processor clock............................................................................
4.3.2
Secondary cache clock .............................................................................................................
4.4
System Configuration Example ........................................................................................
4.4.1
Uni-processor system ...............................................................................................................
4.4.2
Multi-processor system .............................................................................................................
4.5
BTMC Interface....................................................................................................................
4.6
DSD (Delay Speculative Dirty) Mode (V
R
12000 only) .....................................................
4.6.1
DSD mode delay .......................................................................................................................
4.6.2
Secondary cache status in DSD mode ....................................................................................
4.6.3
Other features............................................................................................................................
32
32
32
33
33
33
33
33
33
35
36
38
38
38
38
5.
INTERNAL/EXTERNAL CONTROL FUNCTIONS.......................................................................
5.1
Reset Function ....................................................................................................................
5.1.1
Power-ON reset and cold reset ................................................................................................
5.1.2
Software reset ...........................................................................................................................
5.2
Interrupt Functions .............................................................................................................
5.3
JTAG Function.....................................................................................................................
39
39
39
39
39
40
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