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參數(shù)資料
| 型號： | μPD26411 |
| 廠商： | NEC Corp. |
| 英文描述： | 1M-Bit SRAM and 2M-Bit MASK ROM COMBO Chip(1M位靜態(tài)RAM 和2M位掩膜 ROM) |
| 中文描述： | 100萬位的SRAM和2M位掩膜ROM集成芯片（100萬位靜態(tài)的RAM和200萬位掩膜光盤） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 118K |
| 代理商： | ΜPD26411 |
13
μ
PD26411
RAM Write Cycle Timing Chart (/WE Controlled)
t
AS
t
OW
t
AW
High
impedance
/WE (Input)
/RAMCS (Input)
A0 - A16 (Input)
I/O (Output)
/ROMCS (Input)
t
RAMROM
t
WC
t
RAMCW
Indefinite data out
Data in
t
DH
t
DW
t
WHZ
t
WP
t
WR
Indefinite
data out
High
impedance
t
ROMRAM
Cautions 1. /RAMCS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in
phase with output signals.
Remarks 1.
Write operation is done during the overlap time of a low level /RAMCS and a low level /WE.
2.
When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
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