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參數(shù)資料
| 型號： | ZXCW6100 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 420K |
| 代理商： | ZXCW6100 |
DC Dither
A function is provided to help eliminate small signal
digitalzero pointswitching distortionby theadditionof
a small DC voltage. This is intended to move the signal
away from theDAC zero to preventthedistortionthatis
sometimes discernible when the DAC switches around
zero.
DC Dither would be required when using the
recommended HPWM mode. If using RPWM DC dither
would not normally be set, however, the requirement
is application dependant and full details on use are
available in the associated Application document.
Contact your nearest Zetex office for full details.
Bit 36: 0 = DC dither off, 1 = DC dither on
Digital interface select
Bits 44 and 45 select the digital interface standard
required as below:
00
01
10
11
24 bit I
2
S
Left justify 24 or 32 bit
Right justify 16 bit
Right justify 24 bit
NOVALOAD
NOVALOAD is selected using bits 34 and 35 as
below:
Bit 34: 0 = NOVALOAD off, 1 = NOVALOAD on
Bit 35: 0 = remove bass control if bass clips,
1 = adjust volume control if bass clips
NOVALOAD limiter attack rate
The limiter attack rate is governed by bits 36 to 39. The
code chosen sets the number of word clock periods to
reduce the gain by 0.5dB. The number of word clock
periods quadruples per digital increment.
Code sequence follow:
000
001
010
011
100
101
110
111
=
=
=
=
=
=
=
=
1 word clock period per 0.5dB
4 word clock periods per 0.5dB
16 word clock periods per 0.5dB
64 word clock periods per 0.5dB
256 word clock periods per 0.5dB
1024 word clock periods per 0.5dB
4096 word clock periods per 0.5dB
16384 word clock periods per 0.5dB
The default condition is 0010 which is 4 word clock
periods.
NOVALOAD limiter release rate
Thelimiterreleaserateis governedby bits 40to 43.The
code chosen sets the number of word clock periods to
reduce the gain by 0.5dB. The number of word clock
periods doubles per digital increment
Code examples in the sequence follow:
0000
0001
0010
=
=
=
16 word clock periods per 0.5dB
32 word clock periods per 0.5dB
64 word clock periods per 0.5dB
1110
1111
=
=
262144 word clock periods per 0.5dB
524288 word clock periods per 0.5dB
The defaultcondition is 1010which is 16384word clock
periods.
ATAPI
The ATAPICD-ROM standard for mixing and muting is
supported by bits 46 to 49. The following logic table
defines how the left and right channels are affected by
the codes set on these bits:
The default setting is 1001 which is left channel = L,
right channel = R
ZXCW6100S28
S E M IC O N D U C T O R S
ISSUE 2 - FEBRUARY 2004
18
ATI3
ATI2
ATI1
ATI0
L channel
R channel
0
0
0
0
MUTE
MUTE
0
0
0
1
MUTE
R
0
0
1
0
MUTE
L
0
0
1
1
MUTE
{(L+R)/2}
0
1
0
0
R
MUTE
0
1
0
1
R
R
0
1
1
0
R
L
0
1
1
1
R
{(L+R)/2}
1
0
0
0
L
MUTE
1
0
0
1
L
R
1
0
1
0
L
L
1
0
1
1
L
{(L+R)/2}
1
1
0
0
{(L+R)/2}
MUTE
1
1
0
1
{(L+R)/2}
R
1
1
1
0
{(L+R)/2}
L
1
1
1
1
{(L+R)/2}
{(L+R)/2}
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZXCW6100S28 | 功能描述:IC AMP AUDIO STEREO 25BIT 28SSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 音頻放大器 系列:Acoustar™, NOVALOAD™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:DirectDrive® 類型:H 類 輸出類型:耳機，2-通道（立體聲） 在某負載時最大輸出功率 x 通道數(shù)量:35mW x 2 @ 16 歐姆 電源電壓:1.62 V ~ 1.98 V 特點:I²C，麥克風，靜音，短路保護，音量控制 安裝類型:表面貼裝 供應商設(shè)備封裝:25-WLP（2.09x2.09） 封裝/外殼:25-WFBGA，WLCSP 包裝:帶卷 (TR) |
| ZXCW6100S28_04 | 制造商:ZETEX 制造商全稱:ZETEX 功能描述:24 BIT STEREO DIRECT DRIVE DIGITAL AUDIO AMPLIFIER |
| ZXCW6100S28TC | 功能描述:音頻放大器 24Bit Amp RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| ZXCW8100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32 BIT STEREO DIRECT DRIVE DIGITAL AUDIO AMPLIFIER |
| ZXCW8100S28 | 制造商:ZETEX 制造商全稱:ZETEX 功能描述:32 BIT STEREO DIRECT DRIVE DIGITAL AUDIO AMPLIFIER |
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