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參數(shù)資料
| 型號： | ZR36057PQC |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 228K |
| 代理商： | ZR36057PQC |
ZR36011
PRELIMINARY
6
again starting at the second rising edge of CLK following the
falling edge of OE. Note that since OE enables and disables the
internal clock, it is a synchronous input and must have sufficient
setup and hold time. See Figure 3 for an example of the opera-
tion of OE.
DECIMATION AND INTERPOLATION MODES
The three MODE control pins select the operating mode of the
decimation and interpolation function block, as shown in
Table 1. Decimation is performed in forward color space conver-
sion (DIR = low), and interpolation is performed in inverse color
space conversion (DIR = high).
Whenever decimation or interpolation of the luminance and/or
chrominance data is performed (all modes with the exception of
MODE = 000), each data sample on the Y, CB, CR pins
occupies more than one clock cycle, or the chrominance data is
multiplexed on the CR pins, or both (multiplexed chrominance
samples that occupy more than one clock cycle each). The CHS
input signal must be used, as shown in the timing diagrams for
each of the modes, to synchronize the operation of the device to
the data on the Y, CR, CB pins. The second rising edge of CLK
following the rising edge of CHS always samples the first input
data point. CHS is used to initialize the state of the internal
mechanism that subsequently maintains the synchronization.
MODE = 000
In this mode no decimation or interpolation is performed. YCbCr
pixels are 24 bits wide; the CR pins carry the Cr data and the CB
pins carry the Cb data. A timing diagram for forward conversion
is shown in Figure 3; inverse conversion in this mode has iden-
tical timing, except that the functions of the R, G, B pins are
exchanged with those of the Y, CR, CB pins. The operation of
the OE signal is also depicted in Figure 3. CHS is not used in this
mode of operation.
MODE = 001
In this mode, YCbCr data is in 4:2:2 format. The CB pins are not
used; Cb and Cr data are multiplexed on the CR pins. The Cb
and Cr samples are co-sited with the Y sample that is simulta-
CLK
OE
R, G, B
(Input)
R, G, B
(N)
Y, Cr, Cb
(Output)
Figure 3. RGB to YCbCr Conversion, MODE = 000, also Showing OE Timing
R, G, B
(N+1)
R, G, B
(N+2)
R, G, B
(N+3)
R, G, B
(N+4)
R, G, B
(N+10)
R, G, B
(N+11)
R, G, B
(N+12)
R, G, B
(N+13)
R, G, B
(N+14)
Y, Cr, Cb
(N-8)
Y, Cr, Cb
(N-7)
Y, Cr, Cb
(N-6)
Y, Cr, Cb
(N)
Y, Cr, Cb
(N+1)
Y, Cr, Cb
(N+4)
Y, Cr, Cb
(N+5)
Y, Cr, Cb
(N+6)
neous with the Cb sample. Cb and Cr are decimated in forward
conversion by dropping the unused samples, and interpolated in
inverse conversion by replication. No filtering is performed in
either direction. Figures 4 and 5, respectively, illustrate how the
decimation and interpolation are performed.
CHS determines the validity of input data and synchronizes the
multiplexing of Cr and Cb on the CR pins. As shown in Figure 6
for forward conversion, and Figure 7 for inverse conversion, the
second rising edge of CLK following the rising edge of CHS
latches the first valid input data sample and determines the mul-
tiplex order.
Data Output:
Y
CR
Y (N)
Cb (N)
Y (N+1)
Cr (N)
Y (N+2)
Cb (N+2)
Y (N+3)
Cr (N+2)
Y
Y0
Cr0
Cb0
Cb0
CR
Y1
Cr1
Cb1
Cr0
Y2
Cr2
Cb2
Cb2
Y3
Cr3
Cb3
Cr2
Y4
Cr4
Cb4
Cb4
Y5
Cr5
Cb5
Cr4
Figure 4. Illustration of Decimation Method, MODE = 001
Data Input:
Y
CR
Y (N)
Cb (N)
Y (N+1)
Cr (N)
Y (N+2)
Cb (N+2)
Y (N+3)
Cr (N+2)
Y
Y0
Cb0
Cb0
CR
Y1
Cr0
Y2
Cb2
Cr2
Y3
Cb4
Y4
Y5
Cr4
Figure 5. Illustration of Interpolation Method, MODE = 001
Y (N+4)
Cb (N+4)
Cr0
Cr0
Cb0
Cr2
Cb2
Cr2
Cb2
Cr4
Cb4
Cr4
Cb4
Interpolator Output:
Y (N)
Cr (N)
Cb (N)
Y (N+1)
Cr (N)
Cb (N)
Y (N+2)
Cr (N+2)
Cb (N+2)
Y (N+3)
Cr (N+2)
Cb (N+2)
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