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參數(shù)資料
| 型號： | ZR36055PQC29.5 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 228K |
| 代理商： | ZR36055PQC29.5 |
ZR36011
PRELIMINARY
2
Table 1. Signal Description
Name
Type
Description
V
CC
Power
+5 volt power. All V
CC
pins must be connected to +5 volts.
V
SS
Power
Power supply ground. All V
SS
pins must be connected to ground.
CLK
Input
System clock input. Input data and sync signals are latched on the rising edge of CLK, and output data and sync
signals change state following the rising edge of CLK.
RST
Input
Reset, active low. Must be kept low for at least two clock cycles to reset the device. When active, all stages of the
sync delay lines are initialized to the high state, and the delay line output (SRGB if DIR is high, or SYC if DIR is
low) is high.
R(7-0)
I/O
Red component data if CMY is low, or Cyan if CMY is high. 8 bits unsigned. R is an input if DIR is low, and an
output if DIR is high.
G(7-0)
I/O
Green component data if CMY is low, or Magenta if CMY is high. 8 bits unsigned. G is an input if DIR is low, and
an output if DIR is high.
B(7-0)
I/O
Blue component data if CMY is low, or Yellow if CMY is high. 8 bits unsigned. B is an input if DIR is low, and an
output if DIR is high.
SRGB(1-0)
SYC(1-0)
I/O
Sync delay line inputs and outputs. If DIR is low, SRGB is the input and SYC is the output, and vice versa if DIR
is high. Input level changes appear at the output with a delay of 8 clock cycles. Since the delay line output is ini-
tialized to high by RST, these signals are considered active low.
Y(7-0)
I/O
Luminance component data. 8 bits unsigned. Y is an output if DIR is low, and input if DIR is high.
CB(7-0)
I/O
Blue color difference (Cb) component data. 8 bits unsigned if SIGN is low, or 8 bits two’s complement if SIGN is
high. CB is an output if DIR is low, and input if DIR is high. In 4:2:2 and 4:1:1 modes, CB is unused (if outputs, all
CB pins are high).
CR(7-0)
I/O
Red color difference (Cr) component data. 8 bits unsigned if SIGN is low, or 8 bits two’s complement if SIGN is
high. CR is an output if DIR is low, and input if DIR is high. In 4:2:2 and 4:1:1 modes, Cb and Cr data are multi-
plexed on CR.
DIR
Input
Direction control. If DIR is low, RGB (or CyMaYe) to YCbCr conversion is performed. If DIR is high, YCbCr to RGB
(or CyMaYe) conversion is performed.
CMY
Input
CyMaYe color space control. If CMY is low, conversion between RGB and YCbCr color spaces is performed. If
CMY is high, the R, G and B inputs or outputs are complemented, with the result that conversion between CyMaYe
and YCbCr color spaces is performed.
CCIR
Input
Signal level control. If CCIR is low, input and output data may occupy the full 8 bit signal level range. If CCIR is
high, input and output data signal levels conform to CCIR Recommendation 601-2.
CHS
Input
Chrominance multiplex synchronization signal. The rising edge of this signal is used to synchronize an internal
toggle that controls the multiplexing of the Cb and Cr component data on the CB pins, in the operating modes with
decimated chrominance. In operating modes with decimated luminance, it determines the temporal alignment of
the decimated data.
SIGN
Input
Chrominance numerical representation control. The Cb and Cr data is unsigned if SIGN is low, and two’s comple-
ment if SIGN is high.
OE
Input
Output enable. When low, all outputs are enabled. When high, all outputs are disabled (floating). OE also disables
the internal clock of the device when it is high, thus freezing all internal processing.
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