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參數(shù)資料
| 型號： | ZI9041B |
| 英文描述： | 多中繼系統(tǒng)時鐘芯片 |
| 中文描述： | 多中繼系統(tǒng)時鐘芯片 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大小： | 972K |
| 代理商： | ZI9041B |
Zi9041B
用戶手冊
(20020810).doc
5. Freerun Mode selected.
6. 8kHz Frequency Mode selected.
7. 1.544MHz Frequency Mode selected.
8. 2.048MHz Frequency Mode selected.
9. Master clock input OSCi at 20MHz ±0ppm.
10. Master clock input OSCi at 20MHz ±32ppm.
11. Master clock input OSCi at 20MHz ±100ppm.
12. Selected reference input at ±0ppm.
13. Selected reference input at ±32ppm.
14. Selected reference input at ±100ppm.
15. For Freerun Mode of ±0ppm.
16. For Freerun Mode of ±32ppm.
17. For Freerun Mode of ±100ppm.
18. For capture range of ±230ppm.
19. For capture range of ±198ppm.
20. For capture range of ±130ppm.
21. 25pF capacitive load.
22. OSCi Master Clock jitter is less than 2nspp, or 0.04UIpp where1UIpp=1/20MHz.
23. Jitter on reference input is less than 7nspp.
24. Applied jitter is sinusoidal.
25. Minimum applied input jitter magnitude to regain synchronization.
26. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
27. Within 10ms of the state, reference or input change.
28. 1UIpp = 125us for 8kHz signals.
29. 1UIpp = 648ns for 1.544MHz signals.
30. 1UIpp = 488ns for 2.048MHz signals.
31. 1UIpp = 323ns for 3.088MHz signals.
32. 1UIpp = 244ns for 4.096MHz signals.
33. 1UIpp = 122ns for 8.192MHz signals.
20
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