參數資料
型號: Z84C9008VSC
文件頁數: 30/31頁
文件大?。?/td> 491K
代理商: Z84C9008VSC
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The following describe the limitations of Revision A of the Z84C90 KIO.
!5
Daisy-chain. If the KIO has an Interrupt Pending during and Interrupt Acknowledge
cycle, KIO misses the status of the IE1 pin. This produces vector contention if there is a
higher interrupting device. It works fine if only one device is in the system.
#)85
There is no problem if the application has only one peripheral in the daisy chain. For two
or more peripherals in the system, a
hardware workaround circuit
is needed. Please con-
tact your local Zilog representatives to get more detailed information.
!5
Reset. KIO requires the M1 signal to exit from Reset state. If the M1 signal is not
received, the KIO can not be programmed. This is not a problem for users of the Z80
CPU.
#85
If the CPU is other than a Z80, an M1 signal is needed to exit RESET status. Otherwise,
the KIO can not be programmed.
!5
Port C. When Port C is used as Parallel I/O (not as SIO
s modem signals) and there is a
status change on PC1 or PC6, the status of SYNCA or SYNCB (SIO cell) also changes.
#)85
Before using Port C as a parallel port, set the SIO modem signal mode back to Port C. This
procedure avoids the problem.
!5
Interrupt Acknowledge cycle. The KIO modifies the contents of the KIO control register
(specifically, the KIO modifies the daisy-chain configuration) if the CE pin is active dur-
ing the Interrupt Acknowledge cycle (with other conditions satisfied).
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