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參數(shù)資料
| 型號(hào)： | Z684 |
| 英文描述： | FUSE 3A/125V SUB-MINIATURE PICO |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 5/13頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | Z684 |
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I
Z684 PCI Bus Controller
I
5
OKI SEMICONDUCTOR
MIDSELCS
Input
HIGH
PCI Configuration Cycle Select
registers of a PCI device.
. This signal indicates that the module intends to access configuration
MA[31:0]
Input
–
Module Address Input Bus
Z684. The address is valid when MADSB is asserted LOW.
. The MA[31:0] signals are the 32-bit input address bus from the module to the
MD[31:0]
Input
–
Module Data Input Bus
. The MD[31:0] signals are the 32-bit input data bus from the module to the Z684.
MBEB[3:0]
Input
–
Module Byte Enable
is valid when corresponding MBEB[3:0] bit is asserted LOW.
. The MBEB[3:0] signals select the byte or bytes on the MD[31:0] data bus. The byte
PADSB
Output
LOW
Module Address Strobe Output
PA[31:0] address bus is valid. The PADSB output also signals the beginning of a bus transaction.
. When asserted LOW, the PADSB output signals that the address on the
PBLASTB
Output
LOW
Module Burst Last Output
last data phase.
. When asserted LOW, this signal indicates that the transaction has entered the
PRDYB
Output
LOW
Module Data Ready Output
data bus, MD[31:0].
. This signal indicates that the Z684 has received valid data from the module
PM_IOB
Output
–
Module Memory or I/O Select Output
LOW, I/O access is selected.
. When asserted HIGH, memory access is selected. When asserted
PD_CB
Output
–
Module Data or Code Select Output
cycle. When the Z684 asserts PD_CB LOW, the bus performs a code access cycle.
. When the Z684 asserts PD_CB HIGH, the bus performs a data access
PWR_RDB
Output
–
Module Write or Read Output
Z684 asserts PWR_RDB HIGH, the bus performs a WRITE cycle. When the Z684 asserts PWR_RDB LOW,
the bus performs a read cycle.
. This signal defines whether a write or read bus cycle takes place. When the
PHOLD
Output
HIGH
Module Hold Request Output
asserts PHOLD HIGH. The PHOLD signal is equivalent to the HOLD signal on the i486 bus.
. When the Z684 intends to start a transaction targeting the module, the Z684
PBOFFB
Output
LOW
Module Back-Off Output.
to stop the current transaction.
When asserted LOW, this signal indicates that the Z684 is requesting the module
PA[31:0]
Output
–
Module Address Output
.
This is the address bus output, driven from the Z684 to the module.
PD[31:0]
Output
–
Module Data Output
. The PD[31:0] signals are the 32-bit output data bus from the module to the Z684.
PBEB[3:0]
Output
–
Module Byte Enable Output.
when the corresponding PBEB[3:0] is asserted LOW.
These signals select the valid bytes on the PD[31:0] data bus. The byte is valid
PCS[5:0]
Output
–
PCI-to-Module
registers has been selected.
Chip Select. These outputs indicate that one of the address spaces in the base address
Module Interface Signals
(Continued)
Signal
Type
Assertion
Description
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