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參數(shù)資料
| 型號： | Z0220516SSCR4259 |
| 英文描述： | Modem Controller |
| 中文描述： | 調(diào)制解調(diào)器控制器 |
| 文件頁數(shù)： | 16/48頁 |
| 文件大?。?/td> | 1331K |
| 代理商： | Z0220516SSCR4259 |
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Z02201
V.22bis Data Pump with Integrated AFE
ZiLOG
16
Z02201
PS000902-0501
TRANSMIT LEVELS
The transmit output level of the Z02201 is programmable
in 1 dBm decrements from –6 dBm to –43 dBm. With a
default value of –10 dBm, the Z02201 is measured
differentially across pins TX0+ and TX0– with a sinusoidal
waveform.
Note:
To avoid saturation, the Tx level should be set to –6 dBm
or lower by the host. If a higher transmit level is required,
additional op amps may be added during operation.
RECEIVER LEVELS
The timing recovery circuit can track a
±
0.01% (100 ppm)
frequency error in the associated transmit timing source
with less than 1.0 dB degradation in performance.
Clamping
Received Data (
RXD
) is clamped to a constant mark
whenever
RLSD
is
OFF
.
SOFTWARE INTERFACE
Note:
This section refers to the
Version 0x48
of the datapump
firmware. For various versions of the datapump and the
differences in firmware refer to the addendum of the
product specification.
The host microprocessor communicates with the Z02201
via the parallel microprocessor bus interface. Access is
provided to a set of seven 8-bit Interface Registers, and
through these registers, to Z02201 RAM memory locations.
This interface allows the host to request modem status
information and receive data, control the configuration, and
load data for transmit. Table 10 is the Parallel Interface
Register map.
Microprocessor Interface Register and Bit Definitions:
Reg0, Reg1 RAMDL, RAMDH
—
DATA PUMP RAM
DATA REGISTERS.
In this case,
RAMDL
is the least
significant byte, and RAMDH is the most significant byte.
After a data pump RAM read operation has completed,
these registers contain the requested data. When a data
pump RAM write operation is started, these registers
contain the data written to data pump RAM.
Reg2 RAMAL
—
DATA PUMP RAM DATA ADDRESS.
When a data pump RAM read or write operation is started,
this byte contains the lower 8 bits of the RAM address.
Register 4 (RAMAH) is the high bit of the RAM address.
Reg3 DATAP
—
DATA PUMP PARALLEL DATA.
This
register contains data transferred to or from the remote
modem during the parallel modem (see register Register 4,
bit 4). At any reset, when Config register bits 0–6 (
MODE
)
is
0
(
STANDBY
), the data pump places its firmware version
number in register
DATAP
.
Table 10. Parallel Interface Register Map
Function
RAM Access Low
RAM Access High
RAM Access
Address
Parallel Data
RAM Control &
Status
Modem Status
HDLC
Register
Number
0
1
2
RS2
–
0
b2b1b0
000
001
010
MSB
Bit 7
Bit 6
Bit 5
Bit 4
RAMDL
RAMDH
RAMAL
Bit 3
Bit 2
Bit 1
LSB
Bit 0
Access
Method
R/W
R/W
W
3
4
011
100
DATAP
TPDM
R/W
R/W
TXlE
RXlE
RAMlE
RTSP
RAMRW RAMRQ RAMAH
5
7
101
111
TXI
0
RXI
0
RAMl
0
DPBUSY Reserved
0
RTRND
TEND
CDET
RXERR
RES
EOF
R
0
R/W
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