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參數(shù)資料
| 型號： | Z0220112VSCR3470 |
| 英文描述： | MODEM |
| 中文描述： | 調(diào)制解調(diào)器 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 1331K |
| 代理商： | Z0220112VSCR3470 |
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Z02201
V.22bis Data Pump with Integrated AFE
ZiLOG
14
Z02201
PS000902-0501
HARDWARE INTERFACE SIGNALS
The Z02201 interface consists of the Synchronous Serial
Interface Port, 8-bit Host Microprocessor Interface, Eye
Pattern Interface, Voice Band AFE, System Signals, and
Overhead Signals. The Z02201 functional interconnect
diagram is indicated in Figure 7. Any signal that is active
Low is represented by a line over the signal name.
Synchronous Serial Interface Port
The Synchronous Serial Interface Port provides no parallel-
to-serial/serial-to-parallel conversion hardware. The
synchronous serial interface port consists of six signal pins:
Host Port Interface
The host parallel port interface consists of 15 signal pins:
8-bit bidirectional data bus pins (
HD7
–
HD0
), 3-bit Address
bus (
HA2
–
HA0
), four control lines, which include the Ho
ST
READ
(
HRD
),
HOST
WRITE
(
HWR
),
HOST CHIP SELEC
t
(
HCS
), and
HOST INTERRUPT REQUEST
(
HIRQ
).
Multiple interrupt sources are provided in the Z02201, each
of which can be masked under host control.
The host parallel interface allows the host to access the data
pump RAM address and data bits, transmit and receive data,
control the RAM and status bits, and read data pump status
bits. The host can access eye pattern functions, transmit and
receive tones, and access adaptive equalizer coefficients in
modem-type applications.
The host parallel interface is compatible with standard 8-
bit microprocessors, which include the Z8 and Z80 bus.
Eye Pattern Interface
The eye pattern interface consists of three pins:
EYE
PATTERN DATA
(
EYEOUT
),
EYE PATTERN CLOCK
(
EYECLK
), and
EYE PATTERN STROBE
(
EYESTB
).
Sixteen bits of data are serially transmitted via
EYEOUT
,
under control of
EYESTB
and
EYECLK
. The first byte is the
X-coordinate and the second byte is Y-coordinate of the
sample. The least significant bit is presented first for both
Figure 7. Modem Functional Interconnect Diagram
RXI+,RXI
–
TXO+,TXO
–
Oscilloscope
Data Access
Arrangement
Eye Pattern
Interface
DGND (2)
AGND (2)
+5AVDD (2)
+5VDD (2)
Optional
Optional
EYE Pins (3)
D(0:7)
Crystal
Oscillator
RS(0:2)
Control
Z02201
2
Synchronous
Serial
Interface
8
3
4
6
RESET
XTAL1 XTAL2
Crystal
Oscillator
PSTN
Host
Processor
DTE (Host)
OH
Pin
TxD
RxD
RTS
RLSD
TCLK
RCLK
Signal Name
Transmit Data
Receive Data
Request To Send
Receive Line Signal Detect
Transmit Data Clock
Receive Data Clock
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| Z0220112VSCR3470T | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:V.22BIS Data Pump with INTEGRATED AFE |
| Z0220112VSCR3470TR | 功能描述:IC MODEM CTRL 2400BPS 44PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 調(diào)制解調(diào)器 - IC 和模塊 系列:- 標(biāo)準(zhǔn)包裝:25 系列:- 數(shù)據(jù)格式:V.21，V.22，V.23，V.29，V.32，V.34，V.90，V.92，Bell 103，Bell 212A 波特率:33.6k 電源電壓:3.3V 安裝類型:- 封裝/外殼:- 供應(yīng)商設(shè)備封裝:- 包裝:托盤 配用:591-1013-ND - KIT DEV SOCKETMODEM PARALLEL591-1009-ND - KIT DEV SRL SOCKETMODEM UNIVERSL 其它名稱:MT5656SMI-P-V-34.R2-SPMT5656SMI-P-V-34.R2-SP-NDQ4711574 |
| Z0220112VSCR4078 | 功能描述:電信線路管理 IC MODEM 2400BPS DSP RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| Z0220112VSCR4078T | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:V.22BIS Data Pump with INTEGRATED AFE |
| Z0220112VSCR4078TR | 功能描述:IC MODEM CTRL 2400BPS 44PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 調(diào)制解調(diào)器 - IC 和模塊 系列:- 標(biāo)準(zhǔn)包裝:25 系列:- 數(shù)據(jù)格式:V.21，V.22，V.23，V.29，V.32，V.34，V.90，V.92，Bell 103，Bell 212A 波特率:33.6k 電源電壓:3.3V 安裝類型:- 封裝/外殼:- 供應(yīng)商設(shè)備封裝:- 包裝:托盤 配用:591-1013-ND - KIT DEV SOCKETMODEM PARALLEL591-1009-ND - KIT DEV SRL SOCKETMODEM UNIVERSL 其它名稱:MT5656SMI-P-V-34.R2-SPMT5656SMI-P-V-34.R2-SP-NDQ4711574 |
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