
XRT94L43
9
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
REV. 1.0.2
T22
R22
U24
R21
W26
T25
R25
R26
PDATA_0
PDATA_1
PDATA_2
PDATA_3
PDATA_4
PDATA_5
PDATA_6
PDATA_7
I/O
TTL
Bi-Directional Data Bus Pins (Microprocessor Interface):
These pins are used to drive and receive data over the bi-directional data
bus,, whenever the Microprocessor performs READ or WRITE operations
with the Microprocessor Interface of the XRT94L43.
Y26
WR/
R/W
I
TTL
Write Strobe/Read-Write operation Identifier:
The function of this input pin depends upon which mode the Microproces-
sor Interface has been configured to operate in.
Intel-Asynchronous Mode - WR - Write Strobe Input:
If the Microprocessor Interface is configured to operate in the Intel-Asyn-
chronous Mode, then this input pin functions as the WR (Active Low WRITE
Strobe) input signal from the Microprocessor. Once this active-low signal is
asserted, then the input buffers (associated with the Bi-Directional Data
Bus pin, D[7:0]) will be enabled. The Microprocessor Interface will latch the
contents on the Bi-Directional Data Bus (into the "target" register or address
location, within the XRT94L43) upon the rising edge of this input pin.
Motorola-Asynchronous Mode - R/W - Read/Write Operation Identifi-
cation Input Pin:
If the Microprocessor Interface is operating in the "Motorola-Asynchronous
Mode", then this pin is functionally equivalent to the "R/W" input pin. In the
Motorola Mode, a "READ" operation occurs if this pin is held at a logic "1",
coincident to a falling edge of the RD/DS (Data Strobe) input pin. Similarly
a WRITE operation occurs if this pin is at a logic "0", coincident to a falling
edge of the RD/DS (Data Strobe) input pin.
Power PC 403 Mode - R/W - Read/Write Operation Identification Input:
If the Microprocessor Interface is configured to operate in the Power PC
403 Mode, then this input pin will function as the "Read/Write Operation
Identification Input" pin.
Anytime the Microprocessor Interface samples this input signal at a logic
low (while also sampling the CS input pin "low") upon the rising edge of
μ
PCLK, then the Microprocessor Interface will (upon the very same rising
edge of
μ
PCLK) latch the contents of the Address Bus (A[15:0]) into the
Microprocessor Interface circuitry, in preparation for this forthcoming READ
operation. At some point (later in this READ operation) the Microprocessor
will also assert the DBEN/OE input pin, and the Microprocessor Interface
will then place the contents of the "target" register (or address location
within the XRT94L43) upon the Bi-Directional Data Bus pins (D[7:0]), where
it can be read by the Microprocessor .
Anytime the Microprocessor Interface samples this input signal at a logic
high (while also sampling the CS input pin a logic "low") upon the rising
edge of
μ
PCLK, then the Microprocessor Interface will (upon the very same
rising edge of
μ
PCLK) latch the contents of the Address Bus (A[15:0]) into
the Microprocessor Interface circuitry, in preparation for the forthcoming
WRITE operation. At some point (later in this WRITE operation) the Micro-
processor will also assert the RD/DS/WE input pin, and the Microprocessor
Interface will then latch the contents of the Bi-Directional Data Bus (D[7:0])
into the contents of the "target" register or buffer location (within the
XRT94L43).
MICROPROCESSOR INTERFACE
P
IN
#
S
IGNAL
N
AME
I/O
S
IGNAL
T
YPE
D
ESCRIPTION