參數(shù)資料
型號(hào): XRT91L81IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PBGA196
封裝: 12 X 12 MM, STBGA-196
文件頁(yè)數(shù): 20/40頁(yè)
文件大小: 264K
代理商: XRT91L81IB
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
18
3.5
The PISO is used to convert 622/666MHz parallel input data to 2.488/2.666GHz serial output data which can
interface to an optical module. The PISO bit interleaves parallel input data into a serial bit stream taking the
first bit from TXDI3P/N, then the first bit from TXDI2P/N, and so on as shown in Figure 9.
Transmit Parallel Input to Serial Output (PISO)
3.6
The high-speed serial clock synthesized by the CMU is divided by 4, and the TXPCLKOP/N clock is presented
to an upstream device. The upstream device should use TXPCLKOP/N as its timing source. The Upstream
device then generates the TXCLKIP/N clock that is phase aligned with the transmit data and provides it to the
parallel interface of the transmitter. The data must meet setup and hold times with respect to TXCLKIP/N. The
XRT91L81 will latch TXDI[3:0]P/N on the falling edge of TXCLKIP/N. The clock synthesizer uses a PLL to lock
to the differential input reference clock. It can also be driven by an optional external VCXO for loop timed or
local reference de-jitter applications. As an example the REFCLKP/N input can accept a clock from a LVPECL
crystal oscillator that has a frequency accuracy better than 20ppm in order for the TXCLKOP/N frequency to
have the accuracy required for SONET systems. The other input, VCXO_INP/N can be connected to the
output of a VCXO that can be configured to clean up the recovered received clock in loop timing mode before
being applied to the input of the transmit CMU as a reference clock. In addition, the internal phase/frequency
detector and charge pump, combined with an external VCXO can alternately be used as a jitter attenuator to
de-jitter a noisy system reference clock prior to it being used to time the CMU. Figure 10 provides a detailed
overview of the transmit FIFO in a system interface.
Clock Multiplier Unit (CMU) and Re-Timer
F
IGURE
9. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
PISO
b
0
0
b
0
1
b
0
2
b
0
3
b
0
4
b
0
5
b
0
6
b
0
7
b
1
0
b
1
1
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
2
0
b
2
1
b
2
2
b
2
3
b
2
4
b
2
5
b
2
6
b
2
7
b
3
0
b
3
1
b
3
2
b
3
3
b
3
4
b
3
5
b
3
6
b
3
7
4-bit Parallel LVDS Input Data
TXDI0P/N
TXDI3P/N
TXDI2P/N
TXDI1P/N
TXOP/N
TXCLKIP/N
622MHz
2.488GHz
b
0
0
b
1
0
b
2
0
b
3
0
b
0
1
b
1
1
b
2
1
b
3
1
b
0
2
b
1
2
b
2
2
b
3
2
b
0
3
b
1
3
b
2
3
b
3
3
P
time (0)
相關(guān)PDF資料
PDF描述
XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L82 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L82IB 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L82IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT94L31 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC