參數(shù)資料
型號(hào)： XRT91L32IQTR
廠(chǎng)商： Exar Corporation
文件頁(yè)數(shù)： 10/37頁(yè)
文件大小： 0K
描述： IC TXRX SONET/SDH 8BIT 100QFP
產(chǎn)品變化通告： XRT91L32IQ(TR) Obsolescence 12/Oct/2010
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 帶卷 (TR)
XRT91L32
xr
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.2
16
2.4
External Receive Loop Filter Capacitors
These external loop filter 0.47
μF non-polarized capacitors provide the necessary components to achieve the
required receiver jitter performance. They must be well isolated to prohibit noise entering the CDR block and
should be placed as close to the pins as much as possible. Figure 6 shows the pin connections and external
loop filter components. These two non-polarized capacitors should be of +/- 10% tolerance.
2.5
Loss Of Signal
XRT91L32 supports internal Loss of Signal detection (LOS) and external LOS detection. The internal Loss of
Signal Detector monitors the incoming data stream and if the incoming data stream has no transition
continuously for more than 128 bit periods, Loss of Signal is declared. This LOS detection will be removed
when the circuit detects 16 transitions in a 128 bit period sliding window. Pulling the corresponding DLOSDIS
signal to a high level will disable the internal LOS detection circuit. The external LOS function is supported by
the LOSEXT input. The Single-Ended LVPECL input usually comes from the optical module through an output
usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices the polarity of this signal can be either active "Low" or active "High." LOSEXT is
an active "Low" signal requiring a low level to assert or invoke a forced LOS. The external LOSEXT input pin
and internal LOS detector are gated to control detection and declaration of Loss of Signal (see Figure 7.)
Whenever LOS is internally detected or an external LOS is asserted thru the LOSEXT pin, the XRT91L32 will
automatically force the receive parallel data output to a logic state "0" for the entire duration that a LOS
condition is declared. This acts as a receive data mute upon LOS function to prevent random noise from being
misinterpreted as valid incoming data.
FIGURE 6. EXTERNAL LOOP FILTERS
FIGURE 7. LOS DECLARATION CIRCUIT
CAP2N
CAP1N
0.47uF
non-polarized
CAP2P
CAP1P
0.47uF
non-polarized
Pin 66
Pin 63
Pin 64
Pin 65
Intern al L O S D etect
DLO S D IS
LO SEXT ( SD )
LO S D e cla ration
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