TABLE 6: C<" />
參數(shù)資料
型號(hào)： XRT91L32IQTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 9/37頁(yè)
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH 8BIT 100QFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 帶卷 (TR)
xr
XRT91L32
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
15
TABLE 6: CLOCK AND DATA RECOVERY UNIT PERFORMANCE
Jitter specification is defined using a 12kHz to 1.3/5MHz LP-HP single-pole filter.
1These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUI
rms).
2Required to meet SONET output frequency stability requirements.
2.3.1
Internal Clock and Data Recovery Bypass
Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock.
Asserting the CDRDIS "High" disables the internal Clock and Data Recovery unit and the received serial data
bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of the externally recovered
differential clock XRXCLKIP/N coming from the optical module or an external clock recovery unit. Figure 5
shows the possible internal paths of the recovered clock and data.
NAME
PARAMETER
MIN
TYP
MAX
UNITS
REFDUTY
Reference clock duty cycle
40
60
%
REFJIT
Reference clock jitter (rms) with 19.44 MHz reference1
5
ps
REFJIT
Reference clock jitter (rms) with 77.76 MHz reference1
13
ps
REFTOL
Reference clock frequency tolerance2
-20
+20
ppm
TOLJIT
Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern
0.3
0.4
UI
OCLKFREQ
Frequency output
620
624
MHz
OCLKDUTY
Clock output duty cycle
40
60
%
FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS
RXIP
RXIN
MU
X
CDR
MU
X
CDRDIS
Clk
Data
XRXCLKIP
XRXCLKIN
DATA
CLOCK
SIPO
Div by 8 CLOCK
Parallel DATA
8
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