
xr
XRT91L32
REV. 1.0.3
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
5
CDRREFSEL
LVTTL
I
98
Clock and Data Recover Unit Reference Frequency Select
Selects the Clock and Data Recovery Unit reference frequency
based on the table below.
"Low" = CDR uses CMU’s reference clock
"High" = CDR reference clock from CDRAUXREFCLK
NOTE:
CDRAUXREFCLK requires accuracy of 77.76 MHz
+/- 500ppm.
LOOPTIME
LVTTL
I
5
Loop Timing Mode
When the loop timing mode is activated the external reference
clock to the input of the Retimer is replaced with the high-speed
recovered receive clock from the CDR.
"Low" = Disabled
"High" = Loop timing Activated
CDRDIS
LVTTL
I
23
Clock and Data Recovery Unit Disable
Active "High." Disables internal Clock and Data Recovery unit.
Received serial data bypasses the integrated CDR block.
RXINP/N is then sampled on the rising edge of externally
recovered differential clock XRXCLKIP/N coming from the opti-
cal module.
"Low" = Internal CDR unit is Enabled
"High" = Internal CDR unit is Disabled and Bypassed
RLOOPS
LVTTL
I
1
Serial Remote Loopback
The serial remote loopback mode interconnects the receive
serial data input to the transmit serial data output. If serial
remote loopback is enabled, the 8-bit parallel transmit data
input is ignored while the 8-bit parallel receive data output is
maintained.
"Low" = Disabled
"High" = Serial Remote Loopback Mode Enabled
NOTE: DLOOP and RLOOPS can be enabled simultaneously
to achieve a dual loopback diagnostic feature in normal
operation.
NC
No Connect
-
6,7,13,
14,16,26,
27,32,33,
50,52,57,
61,73,74,
77,78,79,
80,83,90,
96
NOTE: No connect
NAME
LEVEL
TYPE
PIN
DESCRIPTION
CDRREFSEL
STS12/
STS3
CDRAUXREFCLK
FREQUENCY
DATA RATE
0
CDR uses CMU’s reference clock
(see CMUFREQSEL pin)
10
77.76 MHz
STS-3/STM-1
155.52 Mbps
11
77.76 MHz
STS-12/STM-4
622.08 Mbps