參數(shù)資料
型號(hào)： XRT91L30IQTR
廠商： Exar Corporation
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH 8BIT 64QFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-FQFP
供應(yīng)商設(shè)備封裝： 64-PQFP（10x10）
包裝： 帶卷 (TR)
XRT91L30
16
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.2
2.3.1
Internal Clock and Data Recovery Bypass
Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock.
Asserting the CDRDIS "High" disables the internal Clock and Data Recovery unit and the received serial data
bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of the externally recovered
differential clock XRXCLKIP/N coming from the optical module or an external clock recovery unit. Figure 5
shows the possible internal paths of the recovered clock and data.
2.4
External Receive Loop Filter Capacitors
These 0.47
F non-polarized external loop filter capacitors provide the necessary components to achieve the
required receiver jitter performance. They must be well isolated to prohibit noise entering the CDR block and
should be placed as close to the pins as much as possible. Figure 6 shows the pin connections and external
loop filter components. These two non-polarized capacitors should be of +/- 10% tolerance.
2.5
Loss Of Signal
XRT91L30 supports internal Loss of Signal detection (LOS) and external LOS detection. The internal Loss of
Signal Detector monitors the incoming data stream and if the incoming data stream has no transition
continuously for more than 128 bit periods, Loss of Signal is declared. This LOS detection will be removed
when the circuit detects 16 transitions in a 128 bit period sliding window. Pulling the corresponding DLOSDIS
signal to a high level will disable the internal LOS detection circuit. The external LOS function is supported by
the LOSEXT input. The Single-Ended LVPECL input usually comes from the optical module through an output
usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices the polarity of this signal can be either active "Low" or active "High." LOSEXT is
an active "Low" signal requiring a low level to assert or invoke a forced LOS. The external LOSEXT input pin
and internal LOS detector are gated to control detection and declaration of Loss of Signal (see figure 7).
Whenever LOS is internally detected or an external LOS is asserted thru the LOSEXT pin, the XRT91L30 will
automatically force the receive parallel data output to a logic state "0" for the entire duration that a LOS
FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS
FIGURE 6. EXTERNAL LOOP FILTERS
RXIP
RXIN
M
U
X
CDR
M
U
X
CDRDIS
Clk
Data
XRXCLKIP
XRXCLKIN
DATA
CLOCK
SIPO
Div by 8 CLOCK
Parallel DATA
8
CAP2N
CAP1N
0.47uF
non-polarized
CAP2P
CAP1P
0.47uF
non-polarized
pin 42
pin 39
pin 40
pin 41
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L30IQTR-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT91L31 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L31_08 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L31ES 功能描述:總線收發(fā)器 RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L31IQ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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