
xr
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
PRELIMINARY
XRT91L30
REV. P1.0.8
II
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 25
F
IGURE
15. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
PISO ......................................................................................................................... 25
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 26
T
ABLE
14: C
LOCK
M
ULTIPLIER
U
NIT
P
ERFORMANCE
....................................................................................................................... 26
3.7 LOOP TIMING AND CLOCK CONTROL ....................................................................................................... 27
T
ABLE
15: L
OOP
T
IMING
AND
C
LOCK
R
ECOVERY
CONFIGURATIONS
................................................................................................. 27
F
IGURE
16. L
OOP
T
IMING
M
ODE
U
SING
I
NTERNAL
CDR
OR
AN
E
XTERNAL
R
ECOVERED
C
LOCK
....................................................... 28
3.8 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 28
F
IGURE
17. T
RANSMIT
S
ERIAL
O
UTPUT
I
NTERFACE
BLOCK
.............................................................................................................. 28
4.0 DIAGNOSTIC FEATURES ...................................................................................................................29
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 29
F
IGURE
18. S
ERIAL
R
EMOTE
L
OOPBACK
......................................................................................................................................... 29
4.2 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 29
F
IGURE
19. D
IGITAL
L
OCAL
L
OOPBACK
........................................................................................................................................... 29
4.3 ANALOG LOCAL LOOPBACK ...................................................................................................................... 30
F
IGURE
20. A
NALOG
L
OCAL
L
OOPBACK
.......................................................................................................................................... 30
4.4 SPLIT LOOPBACK ......................................................................................................................................... 30
F
IGURE
21. S
PLIT
L
OOPBACK
......................................................................................................................................................... 30
4.5 EYE DIAGRAM ............................................................................................................................................... 31
F
IGURE
22. T
RANSMIT
E
LECTRICAL
O
UTPUT
E
YE
D
IAGRAM
............................................................................................................. 31
4.6 SONET JITTER REQUIREMENTS ................................................................................................................. 31
4.6.1 JITTER TOLERANCE:................................................................................................................................................ 31
F
IGURE
23. GR-253 J
ITTER
T
OLERANCE
M
ASK
.............................................................................................................................. 32
F
IGURE
24. XRT91L30 M
EASURED
J
ITTER
T
OLERANCE
................................................................................................................. 32
4.6.2 JITTER GENERATION................................................................................................................................................ 33
F
IGURE
25. XRT91L30 M
EASURED
E
LECTRICAL
P
HASE
N
OISE
T
RANSMIT
J
ITTER
G
ENERATION
AT
622.08 M
BPS
STS-12/STM4
USING
’1010’
OUTPUT
PATTERN
................................................................................................................................................. 33
5.0 ELECTRICAL CHARACTERISTICS ...................................................................................................34
A
BSOLUTE
M
AXIMUM
RATINGS ..................................................................................................................34
ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS .........................................................34
POWER AND CURRENT DC E
LECTRICAL
C
HARACTERISTICS
....................................................................34
...................................................................................................................................................................34
LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS......................................35
ORDERING INFORMATION ..................................................................................................................36
PACKAGE DIMENSIONS................................................................................................36
R
EVISION
H
ISTORY
......................................................................................................................................37