參數(shù)資料
型號： XRT86VL3X
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 141/149頁
文件大小： 1274K
代理商： XRT86VL3X
XRT86VL3X
134
REV. 1.2.0
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
MICROPROCESSOR INTERFACE I/O TIMING
I
NTEL
I
NTERFACE
T
IMING
- A
SYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum
external glue logic and is compatible with the timings of the 8051 or 80188 family of microprocessors. The ALE
signal can be tied ’HIGH’ if this signal is not available, and the corresponding timing interface is shown in
Figure 117
and
Table 26.
F
IGURE
116. I
NTEL
μP I
NTERFACE
T
IMING
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
W
HEN
ALE
I
S
N
OT
T
IED
’HIGH’
T
ABLE
25: I
NTEL
M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
S
YMBOL
P
ARAMETER
M
IN
M
AX
U
NITS
t
0
Valid Address to CS Falling Edge and ALE Rising
Edge
0
-
ns
t
1
ALE Falling Edge to RD Assert
5
-
ns
t
2
RD Assert to RDY Assert
-
140
ns
NA
RD Pulse Width (t
2
)
140
-
ns
t
3
ALE Falling Edge to WR Assert
5
-
ns
t
4
WR Assert to RDY Assert
-
140
ns
NA
WR Pulse Width (t
4
)
140
-
ns
t
5
ALE Pulse Width(t
5
)
10
ns
CS
ADDR14:0]
ALE
DATA[7:0]
RD
WR
RDY
Valid Data for Readback
Data Available to Write Into the LIU
READ OPERATION
WRITE OPERATION
t
0
t
0
t
1
t
4
t
2
t
3
Valid Address
Valid Address
t
5
t
5
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