
XRT86VL38
38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
GPIO INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
GPIO1_3
GPIO1_2
GPIO1_1
GPIO1_0
B21
G22
AE24
AE22
A19
G18
AA20
AA18
I/O
8
General Purpose Input/Output Pins
Each of these pins can be configured to function as either
a general-purpose input or output pin. The exact function
of these pins depend on whether these GPIO pins are
configured as input or output pins as follows.
If GPIO1_n pins are configured as input pins:
The state of these input pins can be monitored by reading
the GPIO1_n Control Bits (Bit 3-0) within the “General Pur-
pose Input/Output 1 Control Register (address 0x4102).
If GPIO1_n pins are configured as output pins:
The state of these output pins can be controlled by writing
the appropriate value into the GPIO1_n Control Bits (Bit 3-
0) within the “General Purpose Input/Output 1 Control
Register (address 0x4102).
Finally, users can configure a given GPIO1_n pin to be an
input pin by setting the corresponding GPIO1_nDIR Bit
(from Bit 7-4), within the “General Purpose Input/Output 1
Control Register (address 0x4102) to ‘0’.
Conversely, users can configure the GPIO1_ n pin to be
an output pin by setting the corresponding GPIO1_nDIR
Bit (from Bit 7-4), within the “General Purpose Input/Out-
put 1 Control Register (address 0x4102) to ‘1’.
GPIO0_3
GPIO0_2
GPIO0_1
GPIO0_0
AD20
AB18
AD13
AD11
U16
V15
Y11
AB6
I/O
8
General Purpose Input/Output Pins
Each of these pins can be configured to function as either
a general-purpose input or output pin. The exact function
of these pins depend on whether these GPIO pins are
configured as input or output pins as follows.
If GPIO0_n pins are configured as input pins:
The state of these input pins can be monitored by reading
the GPIO0_n Control Bits (Bit 3-0) within the “General Pur-
pose Input/Output 0 Control Register (address 0x0102).
If GPIO0_n pins are configured as output pins:
The state of these output pins can be controlled by writing
the appropriate value into the GPIO0_n Control Bits (Bit 3-
0) within the “General Purpose Input/Output 0 Control
Register (address 0x0102).
Finally, users can configure a given GPIO0_n pin to be an
input pin by setting the corresponding GPIO0_nDIR Bit
(from Bit 7-4), within the “General Purpose Input/Output 0
Control Register (address 0x0102) to ‘0’.
Conversely, users can configure the GPIO0_ n pin to be
an output pin by setting the corresponding GPIO0_nDIR
Bit (from Bit 7-4), within the “General Purpose Input/Out-
put 0 Control Register (address 0x0102) to ‘1’.